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/Zephyr-Core-3.7.0/boards/arm/mps3/
Dmps3_an547_ns.dts88 reg = <0x1000000 DT_SIZE_M(2)>;
100 reg = <0x21000000 DT_SIZE_M(4)>;
108 reg = <0x60000000 DT_SIZE_M(256)
109 0x70000000 DT_SIZE_M(256)
110 0x80000000 DT_SIZE_M(256)
111 0x90000000 DT_SIZE_M(256)
112 0xa0000000 DT_SIZE_M(256)
113 0xb0000000 DT_SIZE_M(256)
114 0xc0000000 DT_SIZE_M(256)
115 0xd0000000 DT_SIZE_M(256)>;
[all …]
Dmps3_an547.dts136 reg = <0x11000000 DT_SIZE_M(2)>;
148 reg = <0x31000000 DT_SIZE_M(4)>;
156 reg = <0x60000000 DT_SIZE_M(256)
157 0x70000000 DT_SIZE_M(256)
158 0x80000000 DT_SIZE_M(256)
159 0x90000000 DT_SIZE_M(256)
160 0xa0000000 DT_SIZE_M(256)
161 0xb0000000 DT_SIZE_M(256)
162 0xc0000000 DT_SIZE_M(256)
163 0xd0000000 DT_SIZE_M(256)>;
/Zephyr-Core-3.7.0/boards/nxp/mimxrt1170_evk/
Dmimxrt1170_evk_mimxrt1176_cm4_B.overlay23 reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>;
26 size = <DT_SIZE_M(64*8)>;
48 reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>;
52 reg = <0x00723000 DT_SIZE_M(7)>;
56 reg = <0x00E23000 (DT_SIZE_M(50) - DT_SIZE_K(140))>;
Dmimxrt1170_evk_mimxrt1176_cm7_B.overlay26 reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>;
29 size = <DT_SIZE_M(64*8)>;
51 reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>;
55 reg = <0x00723000 DT_SIZE_M(7)>;
59 reg = <0x00E23000 (DT_SIZE_M(50) - DT_SIZE_K(140))>;
/Zephyr-Core-3.7.0/boards/nxp/mimxrt1050_evk/
Dmimxrt1050_evk_mimxrt1052_hyperflash.overlay26 reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>;
29 size = <DT_SIZE_M(64*8)>;
58 reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(56))>;
62 reg = <0x0032E000 DT_SIZE_M(3)>;
66 reg = <0x0062E000 (DT_SIZE_M(58) - DT_SIZE_K(184))>;
Dmimxrt1050_evk_mimxrt1052_qspi.overlay20 reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
43 reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>;
47 reg = <0x00322000 DT_SIZE_M(3)>;
51 reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>;
/Zephyr-Core-3.7.0/boards/nxp/mimxrt1060_evk/
Dmimxrt1060_evk_mimxrt1062_hyperflash.overlay24 reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>;
27 size = <DT_SIZE_M(64*8)>;
56 reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(56))>;
60 reg = <0x0032E000 DT_SIZE_M(3)>;
64 reg = <0x0062E000 (DT_SIZE_M(58) - DT_SIZE_K(184))>;
Dmimxrt1060_evk_mimxrt1062_qspi.overlay22 reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
46 reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>;
50 reg = <0x00322000 DT_SIZE_M(3)>;
54 reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>;
/Zephyr-Core-3.7.0/dts/xtensa/espressif/esp32s2/
Desp32s2_mini_n4r2.dtsi11 reg = <0x0 DT_SIZE_M(4)>;
17 reg = <0x3f500000 DT_SIZE_M(2)>;
Desp32s2_wrover_n16r2.dtsi11 reg = <0x0 DT_SIZE_M(16)>;
17 reg = <0x3f500000 DT_SIZE_M(2)>;
Desp32s2_wrover_n4r2.dtsi11 reg = <0x0 DT_SIZE_M(4)>;
17 reg = <0x3f500000 DT_SIZE_M(2)>;
Desp32s2_fn4r2.dtsi11 reg = <0x0 DT_SIZE_M(4)>;
16 reg = <0x3f500000 DT_SIZE_M(2)>;
Desp32s2_solo_n4r2.dtsi11 reg = <0x0 DT_SIZE_M(4)>;
17 reg = <0x3f500000 DT_SIZE_M(2)>;
Desp32s2_wrover_n8r2.dtsi11 reg = <0x0 DT_SIZE_M(8)>;
17 reg = <0x3f500000 DT_SIZE_M(2)>;
/Zephyr-Core-3.7.0/dts/xtensa/espressif/esp32s3/
Desp32s3_mini_n4r2.dtsi11 reg = <0x0 DT_SIZE_M(4)>;
16 reg = <0x3c000000 DT_SIZE_M(2)>;
Desp32s3_pico_n8r2.dtsi11 reg = <0x0 DT_SIZE_M(8)>;
16 reg = <0x3c000000 DT_SIZE_M(2)>;
Desp32s3_pico_n8r8.dtsi11 reg = <0x0 DT_SIZE_M(8)>;
16 reg = <0x3c000000 DT_SIZE_M(8)>;
Desp32s3_wroom_n16r2.dtsi11 reg = <0x0 DT_SIZE_M(16)>;
16 reg = <0x3c000000 DT_SIZE_M(2)>;
Desp32s3_wroom_n16r8.dtsi11 reg = <0x0 DT_SIZE_M(16)>;
16 reg = <0x3c000000 DT_SIZE_M(8)>;
Desp32s3_wroom_n4r2.dtsi11 reg = <0x0 DT_SIZE_M(4)>;
16 reg = <0x3c000000 DT_SIZE_M(2)>;
Desp32s3_wroom_n4r8.dtsi11 reg = <0x0 DT_SIZE_M(4)>;
16 reg = <0x3c000000 DT_SIZE_M(8)>;
Desp32s3_wroom_n8r2.dtsi11 reg = <0x0 DT_SIZE_M(8)>;
16 reg = <0x3c000000 DT_SIZE_M(2)>;
Desp32s3_wroom_n8r8.dtsi11 reg = <0x0 DT_SIZE_M(8)>;
16 reg = <0x3c000000 DT_SIZE_M(8)>;
/Zephyr-Core-3.7.0/dts/xtensa/espressif/esp32/
Desp32_pico_v3_02.dtsi17 reg = <0x0 DT_SIZE_M(8)>;
22 reg = <0x3f800000 DT_SIZE_M(2)>;
/Zephyr-Core-3.7.0/boards/snps/nsim/arc_classic/
Dnsim-flash-sram-mem.dtsi10 #define DT_FLASH_SIZE DT_SIZE_M(4)
11 #define DT_SRAM_SIZE DT_SIZE_M(4)

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