| /Zephyr-Core-3.5.0/samples/subsys/usb/cdc_acm/ |
| D | sample.yaml | 12 - "Wait for DTR"
25 - "Wait for DTR"
37 - "Wait for DTR"
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| D | README.rst | 58 Wait for DTR
71 DTR set, start test
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| /Zephyr-Core-3.5.0/samples/subsys/usb/cdc_acm_composite/src/ |
| D | main.c | 120 uint32_t dtr = 0U; in main() local
137 LOG_INF("Wait for DTR"); in main()
140 uart_line_ctrl_get(peers[0].dev, UART_LINE_CTRL_DTR, &dtr); in main()
141 if (dtr) { in main()
149 uart_line_ctrl_get(peers[1].dev, UART_LINE_CTRL_DTR, &dtr); in main()
150 if (dtr) { in main()
157 LOG_INF("DTR set, start test"); in main()
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| /Zephyr-Core-3.5.0/samples/subsys/usb/console/src/ |
| D | main.c | 81 uint32_t dtr = 0; in main() local
93 /* Poll if the DTR flag was set */ in main()
94 while (!dtr) { in main()
95 uart_line_ctrl_get(dev, UART_LINE_CTRL_DTR, &dtr); in main()
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| /Zephyr-Core-3.5.0/tests/drivers/uart/uart_basic_api/src/ |
| D | main.c | 52 uint32_t dtr = 0; in uart_basic_setup() local
59 while (!dtr) { in uart_basic_setup()
60 uart_line_ctrl_get(dev, UART_LINE_CTRL_DTR, &dtr); in uart_basic_setup()
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| /Zephyr-Core-3.5.0/samples/subsys/usb/cdc_acm/src/ |
| D | main.c | 156 uint32_t baudrate, dtr = 0U; in main() local
178 LOG_INF("Wait for DTR"); in main()
181 uart_line_ctrl_get(dev, UART_LINE_CTRL_DTR, &dtr); in main()
182 if (dtr) { in main()
190 LOG_INF("DTR set"); in main()
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| /Zephyr-Core-3.5.0/arch/arc/arcmwdt/ |
| D | CMakeLists.txt | 4 zephyr_sources(arcmwdt-dtr-stubs.c)
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| /Zephyr-Core-3.5.0/samples/subsys/usb/cdc_acm_composite/ |
| D | README.rst | 39 Wait for DTR
53 DTR set, start test
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| D | sample.yaml | 17 - "Wait for DTR"
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| /Zephyr-Core-3.5.0/drivers/flash/ |
| D | Kconfig.mcux | 73 or Octal I/O DTR).
79 bool "DTR"
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| D | flash_stm32_ospi.c | 141 int data_rate; /* DTR or STR */
526 * and nor_rate transfer STR/DTR OSPI_STR_TRANSFER or OSPI_DTR_TRANSFER
577 * and nor_rate transfer STR/DTR OSPI_STR_TRANSFER or OSPI_DTR_TRANSFER
779 /* Set the NOR Flash to desired Interface mode : SPI/OSPI and STR/DTR according to the DTS */
793 /* Going to set the OPI mode (STR or DTR transfer rate) */ in stm32_ospi_config_mem()
819 /* Write Configuration register 2 (with Octal I/O SPI protocol : choose STR or DTR) */ in stm32_ospi_config_mem()
866 LOG_INF("OSPI flash config is OPI / DTR"); in stm32_ospi_config_mem()
872 /* gpio or send the different reset command to the NOR flash in SPI/OSPI and STR/DTR */
884 /* Reset command sent sucessively for each mode SPI/OPS & STR/DTR */ in stm32_ospi_mem_reset()
934 /* Reset enable in OPI mode and DTR transfer mode */ in stm32_ospi_mem_reset()
[all …]
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| /Zephyr-Core-3.5.0/tests/bluetooth/shell/src/ |
| D | main.c | 128 uint32_t dtr = 0; in main() local
135 while (!dtr) { in main()
136 uart_line_ctrl_get(dev, UART_LINE_CTRL_DTR, &dtr); in main()
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| /Zephyr-Core-3.5.0/samples/subsys/modbus/rtu_server/src/ |
| D | main.c | 148 uint32_t dtr = 0; in main() local
154 while (!dtr) { in main()
155 uart_line_ctrl_get(dev, UART_LINE_CTRL_DTR, &dtr); in main()
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| /Zephyr-Core-3.5.0/subsys/shell/backends/ |
| D | shell_uart.c | 108 "DTR check requires CONFIG_UART_LINE_CTRL"); in uart_dtr_check()
111 int dtr, err; in uart_dtr_check() local
113 err = uart_line_ctrl_get(dev, UART_LINE_CTRL_DTR, &dtr); in uart_dtr_check()
118 return dtr; in uart_dtr_check()
132 /* DTR is active, stop timer and start TX */ in dtr_timer_handler()
144 /* Wait for DTR signal before sending anything to output. */ in uart_tx_handle()
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| D | Kconfig.backends | 80 bool "Check DTR signal before TX"
84 Check DTR signal before TX.
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| /Zephyr-Core-3.5.0/dts/bindings/modem/ |
| D | quectel,bg9x.yaml | 18 mdm-dtr-gpios:
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| /Zephyr-Core-3.5.0/dts/bindings/serial/ |
| D | espressif,esp32-uart.yaml | 22 Using this mode, the pin assigned to DTR
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| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | spi_xlnx_axi_quadspi.c | 234 uint32_t dtr = 0U; in xlnx_quadspi_start_tx() local
266 dtr = UNALIGNED_GET((uint8_t *)(ctx->tx_buf)); in xlnx_quadspi_start_tx()
269 dtr = UNALIGNED_GET((uint16_t *)(ctx->tx_buf)); in xlnx_quadspi_start_tx()
272 dtr = UNALIGNED_GET((uint32_t *)(ctx->tx_buf)); in xlnx_quadspi_start_tx()
279 dtr = 0U; in xlnx_quadspi_start_tx()
282 xlnx_quadspi_write32(dev, dtr, SPI_DTR_OFFSET); in xlnx_quadspi_start_tx()
453 /* Enable DTR Empty interrupt */ in xlnx_quadspi_init()
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| /Zephyr-Core-3.5.0/samples/boards/esp32/light_sleep/ |
| D | README.rst | 68 check DTR/RTS configuration in the serial monitor. This is not necessary for
69 IDF monitor, but for other tools it might be necessary to set DTR and RTS line
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| /Zephyr-Core-3.5.0/modules/openthread/platform/ |
| D | uart.c | 173 uint32_t dtr = 0U; in otPlatUartEnable() local
184 while (!dtr) { in otPlatUartEnable()
186 UART_LINE_CTRL_DTR, &dtr); in otPlatUartEnable()
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/flash_controller/ |
| D | ospi.h | 14 * OPI mode in DTR transfer rate
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| /Zephyr-Core-3.5.0/dts/bindings/flash_controller/ |
| D | st,stm32-ospi-nor.yaml | 13 data-rate = <OSPI_DTR_TRANSFER>; /* access in DTR */
58 The SPI data Rate is STR or DTR
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| /Zephyr-Core-3.5.0/samples/net/wpan_serial/src/ |
| D | main.c | 531 uint32_t baudrate, dtr = 0U; in main() local
547 LOG_DBG("Wait for DTR"); in main()
550 uart_line_ctrl_get(uart_dev, UART_LINE_CTRL_DTR, &dtr); in main()
551 if (dtr) { in main()
559 LOG_DBG("DTR set, continue"); in main()
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| /Zephyr-Core-3.5.0/samples/boards/sensortile_box/src/ |
| D | main.c | 257 uint32_t dtr = 0; in main() local
264 /* Poll if the DTR flag was set, optional */ in main()
265 while (!dtr) { in main()
266 uart_line_ctrl_get(dev, UART_LINE_CTRL_DTR, &dtr); in main()
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| /Zephyr-Core-3.5.0/samples/drivers/jesd216/ |
| D | README.rst | 35 DTR Clocking not supported
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