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/Zephyr-Core-3.6.0/subsys/dsp/
DKconfig4 menuconfig DSP config
5 bool "DSP subsystem"
7 Include the DSP (Digital Signal Processing) subsystem as a part of the
9 <zephyr/dsp/dsp.h> header.
11 if DSP
23 prompt "DSP library backend selection"
29 bool "Use the CMSIS-DSP library as the math backend"
33 Implement the various zephyr DSP functions using the CMSIS-DSP library. This feature
37 bool "Do not use any Zephyr backends for DSP"
39 Rely on the application to provide a custom DSP backend. The implementation should be
[all …]
/Zephyr-Core-3.6.0/arch/arc/core/dsp/
DKconfig1 # Digital Signal Processing (DSP) configuration options
6 menu "ARC DSP Options"
10 bool "digital signal processing (DSP)"
12 This option enables DSP and DSP instructions.
15 bool "Turn off DSP if it presents"
18 This option disables DSP block via resetting DSP_CRTL register.
21 bool "DSP register sharing"
25 This option enables preservation of the hardware DSP registers
27 DSP operations.
30 bool "ARC complex DSP operation"
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/Zephyr-Core-3.6.0/doc/services/dsp/
Dindex.rst3 Digital Signal Processing (DSP)
10 The DSP API provides an architecture agnostic way for signal processing.
49 added to :file:`subsys/dsp/Kconfig` along with the required dependencies and the
52 Next, the implementation should be added at ``subsys/dsp/<backend>/`` and
53 linked in at :file:`subsys/dsp/CMakeLists.txt`. To add architecture-specific attributes,
54 its corresponding Kconfig option should be added to :file:`subsys/dsp/Kconfig` and use
55 them to update ``DSP_DATA`` and ``DSP_STATIC_DATA`` in :file:`include/zephyr/dsp/dsp.h`.
62 .. _subsys/dsp/Kconfig: https://github.com/zephyrproject-rtos/zephyr/blob/main/subsys/dsp/Kconfig
63 .. _subsys/dsp/CMakeLists.txt: https://github.com/zephyrproject-rtos/zephyr/blob/main/subsys/dsp/CM…
64 .. _include/zephyr/dsp/dsp.h: https://github.com/zephyrproject-rtos/zephyr/blob/main/include/zephyr…
/Zephyr-Core-3.6.0/include/zephyr/dsp/
Ddsp.h6 * @file zephyr/dsp/dsp.h
8 * @brief Public APIs for Digital Signal Processing (DSP) math.
33 * @brief DSP Interface
34 * @defgroup math_dsp DSP Interface
37 #include <zephyr/dsp/types.h>
39 #include <zephyr/dsp/basicmath.h>
41 #include <zephyr/dsp/print_format.h>
/Zephyr-Core-3.6.0/tests/lib/cmsis_dsp/transform/
Dtestcase.yaml5 tags: cmsis-dsp
15 tags: cmsis-dsp
27 - cmsis-dsp
43 tags: cmsis-dsp
55 - cmsis-dsp
71 tags: cmsis-dsp
81 - cmsis-dsp
97 tags: cmsis-dsp
107 - cmsis-dsp
122 tags: cmsis-dsp
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/Zephyr-Core-3.6.0/tests/arch/arc/arc_dsp_sharing/src/
Dload_store.c9 * @brief load/store portion of DSP sharing test
13 * This module implements the load/store portion of the DSP sharing test. This
16 * The load/store test validates the dsp unit context
18 * priorities that each use the dsp registers. The context
20 * the dsp registers. The test also exercises the kernel's ability
21 * to automatically enable dsp support for a task, if supported.
31 /* space for dsp register load/store area used by low priority task */
35 /* space for dsp register load/store area used by high priority thread */
48 * @brief Low priority DSP load/store thread
63 * Initialize dsp load buffer to known values; in load_store_low()
[all …]
Ddsp_regs_arc.h9 * @brief ARC specific dsp register macros
20 * @brief Load all dsp registers
22 * This function loads all DSP and AGU registers pointed to by @a regs.
24 * will be issued to dump the dsp registers to memory.
45 * @brief Dump all dsp registers to memory
47 * This function stores all DSP and AGU registers to the memory buffer
49 * _load_all_dsp_registers() occurred to load all the dsp
65 * @brief Load then dump all dsp registers to memory
67 * This function loads all DSP and AGU registers from the memory buffer
Ddsp_context.h9 * @brief common definitions for the DSP sharing test application
26 /* No non-volatile dsp registers */
32 /* the set of ALL dsp registers */
44 * task, and the thread when loading up the dsp registers.
/Zephyr-Core-3.6.0/tests/lib/cmsis_dsp/matrix/
Dtestcase.yaml5 tags: cmsis-dsp
15 tags: cmsis-dsp
28 - cmsis-dsp
44 tags: cmsis-dsp
57 - cmsis-dsp
73 tags: cmsis-dsp
86 - cmsis-dsp
101 tags: cmsis-dsp
114 - cmsis-dsp
130 tags: cmsis-dsp
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/Zephyr-Core-3.6.0/drivers/counter/
DKconfig.ace6 bool "DSP ART Wall Clock for ACE V1X"
10 DSP ART Wall Clock used by ACE V1X.
13 bool "DSP RTC Wall Clock for ACE V1X"
17 DSP RTC Wall Clock used by ACE V1X.
/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/tools/
Dacetool.py164 # starts before it's ready and kills the load (and often the DSP).
167 # the DSP!
187 log.info(f"Enabling dsp capture (PROCEN) of stream {self.stream_id}")
252 # Intel ACE Audio DSP Registers
255 dsp = Regs(bar4_mem)
256 dsp.HFDSSCS = 0x1000
257 dsp.HFPWRCTL = 0x1d18
258 dsp.HFPWRSTS = 0x1d1c
259 dsp.DSP2CXCTL_PRIMARY = 0x178d04
260 dsp.HFIPCXTDR = 0x73200
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Dcavstool.py160 # starts before it's ready and kills the load (and often the DSP).
163 # the DSP!
183 log.info(f"Enabling dsp capture (PROCEN) of stream {self.stream_id}")
246 # Intel Audio DSP Registers
249 dsp = Regs(bar4_mem)
250 dsp.ADSPCS = 0x00004
251 dsp.HIPCTDR = 0x00040 if cavs15 else 0x000c0
252 dsp.HIPCTDA = 0x000c4 # 1.8+ only
253 dsp.HIPCTDD = 0x00044 if cavs15 else 0x000c8
254 dsp.HIPCIDR = 0x00048 if cavs15 else 0x000d0
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/Zephyr-Core-3.6.0/soc/arm/xilinx_zynq7000/xc7zxxx/
DKconfig.soc17 28k logic cells, 2.1Mb block RAM, 800 DSP slices, up to 100 I/O pins.
23 74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins,
30 85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins.
36 125k logic cells, 9.3Mb block RAM, 400 DSP slices, up to 250 I/O pins,
43 275k logic cells, 17.6Mb block RAM, 900 DSP slices, up to 362 I/O pins,
50 350k logic cells, 19.1Mb block RAM, 900 DSP slices, up to 362 I/O pins,
57 444k logic cells, 26.5Mb block RAM, 2020 DSP slices, up to 400 I/O pins,
/Zephyr-Core-3.6.0/tests/lib/cmsis_dsp/filtering/
Dtestcase.yaml8 tags: cmsis-dsp
31 - cmsis-dsp
47 tags: cmsis-dsp
60 - cmsis-dsp
76 tags: cmsis-dsp
89 - cmsis-dsp
105 tags: cmsis-dsp
119 - cmsis-dsp
/Zephyr-Core-3.6.0/drivers/dai/intel/ssp/
Ddai-params-intel-ipc4.h16 /**< HD/A host output (-> DSP). */
18 /**< HD/A host input (<- DSP). */
23 /**< HD/A link output (DSP ->). */
25 /**< HD/A link input (DSP <-). */
30 /**< DMIC link input (DSP <-). */
33 /**< I2S link output (DSP ->). */
35 /**< I2S link input (DSP <-). */
38 /**< ALH link output, legacy for SNDW (DSP ->). */
40 /**< ALH link input, legacy for SNDW (DSP <-). */
43 /**< SNDW link output (DSP ->). */
[all …]
/Zephyr-Core-3.6.0/include/zephyr/arch/arc/v2/dsp/
Darc_dsp.h10 * @brief Disable dsp context preservation
12 * The function is used to disable the preservation of dsp
25 * @brief Enable dsp context preservation
27 * The function is used to enable the preservation of dsp
/Zephyr-Core-3.6.0/tests/boards/intel_adsp/hda/src/
Dsmoke.c70 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, STREAM_ID, "dsp init"); in ZTEST()
81 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, STREAM_ID, "dsp set_buffer"); in ZTEST()
85 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, STREAM_ID, "dsp enable"); in ZTEST()
93 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, STREAM_ID, "dsp inc_pos"); in ZTEST()
97 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, STREAM_ID, "dsp wp == rp"); in ZTEST()
112 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, STREAM_ID, "dsp disable"); in ZTEST()
134 hda_dump_regs(HOST_OUT, HDA_REGBLOCK_SIZE, STREAM_ID, "dsp init"); in ZTEST()
145 hda_dump_regs(HOST_OUT, HDA_REGBLOCK_SIZE, STREAM_ID, "dsp set buffer"); in ZTEST()
152 hda_dump_regs(HOST_OUT, HDA_REGBLOCK_SIZE, STREAM_ID, "dsp enable"); in ZTEST()
166 hda_dump_regs(HOST_OUT, HDA_REGBLOCK_SIZE, STREAM_ID, "dsp wait for full"); in ZTEST()
[all …]
/Zephyr-Core-3.6.0/drivers/mm/
DKconfig31 bool "Intel Audio DSP TLB Driver for Meteor Lake"
37 Intel Audio DSP hardware (Meteor Lake).
40 bool "Intel Audio DSP TLB Driver"
45 Intel Audio DSP hardware.
/Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/common/include/
Dcavs-idc.h13 * interrupts directly between DSP cores. The interface
61 * level 2 bit for IDC in the per-core INTCTRL DSP register AND the
115 #define CAVS_L2_DWCT1 BIT(23) /* DSP Wall Clock Timer 1 */
116 #define CAVS_L2_DWCT0 BIT(22) /* DSP Wall Clock Timer 0 */
118 #define CAVS_L2_DTS BIT(20) /* DSP Timestamping */
127 #define CAVS_L3_DSPGCL BIT(31) /* DSP Gateway Code Loader */
128 #define CAVS_L3_DSPGHOS(n) BIT(16 + n) /* DSP Gateway Host Output Stream */
130 #define CAVS_L3_DSPGHIS(n) BIT(n) /* DSP Gateway Host Input Stream */
132 #define CAVS_L4_DSPGLOS(n) BIT(16 + n) /* DSP Gateway Link Output Stream */
134 #define CAVS_L4_DSPGLIS(n) BIT(n) /* DSP Gateway Link Input Stream */
[all …]
/Zephyr-Core-3.6.0/soc/arm/xilinx_zynq7000/xc7zxxxs/
DKconfig.soc17 23k logic cells, 1.8 Mb block RAM, 60 DSP slices, up to 100 I/O pins.
23 55k logic cells, 2.5Mb block RAM, 120 DSP slices, up to 150 I/O pins,
30 65k logic cells, 3.8Mb block RAM, 170 DSP slices, up to 200 I/O pins.
/Zephyr-Core-3.6.0/soc/xtensa/nxp_adsp/imx8ulp/
DKconfig.soc5 prompt "NXP i.MX8ULP Audio DSP Selection"
9 bool "NXP i.MX8ULP Audio DSP"
DKconfig.series5 bool "NXP i.MX8ULP Audio DSP Series"
15 Enable support for NXP i.MX8ULP Audio DSP
/Zephyr-Core-3.6.0/drivers/watchdog/
Dwdt_intel_adsp.h18 * DSP Core Watch Dog Timer Control & Status
23 * This register controls the DSP Core watch dog timer policy.
49 * When set, it allow the DSP Core reset to take place upon second time out of the
56 * DSP Core Watch Dog Timer IP Pointer
61 * This register provides the pointer to the DSP Core watch dog timer IP registers.
122 * When set, it allow the DSP Core reset to take place upon second time out of the watchdog timer.
136 * When set, it allow the DSP Core reset to take place upon second time out of the
/Zephyr-Core-3.6.0/soc/xtensa/nxp_adsp/imx8m/
DKconfig.series5 bool "NXP i.MX8M Audio DSP Series"
15 Enable support for NXP i.MX8M Audio DSP
/Zephyr-Core-3.6.0/soc/xtensa/nxp_adsp/imx8/
DKconfig.soc9 bool "NXP i.MX8QM Audio DSP"
14 bool "NXP i.MX8QXP Audio DSP"

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