| /hal_nxp-latest/mcux/mcux-sdk/components/srtm/srtm/ |
| D | srtm_peercore.c | 36 srtm_peercore_t core = (srtm_peercore_t)SRTM_Heap_Malloc(sizeof(struct _srtm_peercore)); in SRTM_PeerCore_Create() local
38 srtm_mutex_t mutex = SRTM_Mutex_Create(&core->mutexStatic); in SRTM_PeerCore_Create()
43 assert((core != NULL) && (mutex != NULL)); in SRTM_PeerCore_Create()
46 SRTM_List_Init(&core->node); in SRTM_PeerCore_Create()
47 SRTM_List_Init(&core->channels); in SRTM_PeerCore_Create()
48 SRTM_List_Init(&core->pendingQ); in SRTM_PeerCore_Create()
50 core->id = id; in SRTM_PeerCore_Create()
51 core->dispatcher = NULL; in SRTM_PeerCore_Create()
52 core->mutex = mutex; in SRTM_PeerCore_Create()
53 core->started = false; in SRTM_PeerCore_Create()
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| D | srtm_dispatcher.c | 100 /* Dequeue message might detach message from messageQ, peer core's pendingQ or waitingReqs */
249 srtm_peercore_t core; in SRTM_Dispatcher_Destroy() local
267 core = SRTM_LIST_OBJ(srtm_peercore_t, node, list); in SRTM_Dispatcher_Destroy()
268 SRTM_PeerCore_Destroy(core); in SRTM_Dispatcher_Destroy()
336 srtm_peercore_t core; in SRTM_Dispatcher_Run() local
351 core = SRTM_LIST_OBJ(srtm_peercore_t, node, list); in SRTM_Dispatcher_Run()
352 (void)SRTM_PeerCore_Start(core); in SRTM_Dispatcher_Run()
377 core = SRTM_LIST_OBJ(srtm_peercore_t, node, list); in SRTM_Dispatcher_Run()
378 (void)SRTM_PeerCore_Stop(core); in SRTM_Dispatcher_Run()
386 srtm_status_t SRTM_Dispatcher_AddPeerCore(srtm_dispatcher_t disp, srtm_peercore_t core) in SRTM_Dispatcher_AddPeerCore() argument
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| /hal_nxp-latest/mcux/mcux-sdk/components/srtm/include/ |
| D | srtm_peercore.h | 23 * @brief SRTM peer core state
27 SRTM_PeerCore_State_Inactive = 0x00U, /*!< Peer core is not ready to communicate */
28 SRTM_PeerCore_State_Activating, /*!< Peer core wakeup in progress */
29 SRTM_PeerCore_State_Activated, /*!< Peer core is ready to communicate */
30 SRTM_PeerCore_State_Deactivating, /*!< Peer core is going to suspend */
31 SRTM_PeerCore_State_Deactivated, /*!< Peer core suspended and not ready to communicate */
35 * @brief SRTM peer core wakeup callback function
37 typedef srtm_status_t (*srtm_peercore_wakeup_cb_t)(srtm_peercore_t core, void *param);
47 * @brief Create SRTM peer core object.
49 * @param id SRTM peer core ID allocated by application.
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_MC_ME.h | 81 …__IO uint32_t PRTN0_CORE0_PCONF; /**< Partition 0 Core 0 Process Configuration Reg…
82 …__IO uint32_t PRTN0_CORE0_PUPD; /**< Partition 0 Core 0 Process Update Register, …
83 …__I uint32_t PRTN0_CORE0_STAT; /**< Partition 0 Core 0 Status Register, offset: …
84 …__IO uint32_t PRTN0_CORE0_ADDR; /**< Partition 0 Core 0 Address Register, offset:…
86 …__IO uint32_t PRTN0_CORE1_PCONF; /**< Partition 0 Core 1 Process Configuration Reg…
87 …__IO uint32_t PRTN0_CORE1_PUPD; /**< Partition 0 Core 1 Process Update Register, …
88 …__I uint32_t PRTN0_CORE1_STAT; /**< Partition 0 Core 1 Status Register, offset: …
89 …__IO uint32_t PRTN0_CORE1_ADDR; /**< Partition 0 Core 1 Address Register, offset:…
91 …__IO uint32_t PRTN0_CORE2_PCONF; /**< Partition 0 Core 2 Process Configuration Reg…
92 …__IO uint32_t PRTN0_CORE2_PUPD; /**< Partition 0 Core 2 Process Update Register, …
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| D | S32Z2_MSCM.h | 76 __I uint32_t CPXTYPE; /**< Core Processor x Type, offset: 0x0 */
77 __I uint32_t CPXNUM; /**< Core Processor x Number, offset: 0x4 */
78 __I uint32_t CPXREV; /**< Core Processor x Revision, offset: 0x8 */
79 …__I uint32_t CPXCFG0; /**< Core Processor x Configuration 0, offset: 0x…
80 …__I uint32_t CPXCFG1; /**< Core or Cluster Processor x Configuration 1,…
81 …__I uint32_t CPXCFG2; /**< Core Processor x Configuration 2, offset: 0x…
82 …__I uint32_t CPXCFG3; /**< Core Processor x Configuration 3, offset: 0x…
86 __I uint32_t CP0REV; /**< Core Processor 0 Revision, offset: 0x28 */
87 …__I uint32_t CP0CFG0; /**< Core Processor 0 Configuration 0, offset: 0x…
89 …__I uint32_t CP0CFG2; /**< Core Processor 0 Configuration 2, offset: 0x…
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/mu/ |
| D | fsl_mu.c | 162 * brief Triggers interrupts to the other core.
164 * This function triggers the specific interrupts to the other core. The interrupts
166 * The MU should not trigger an interrupt to the other core when the previous interrupt
167 * has not been processed by the other core. This function checks whether the
174 * has not been processed by the other core.
206 * brief Boots the core at B side.
208 * This function sets the B side core's boot configuration and releases the
209 * core from reset.
212 * param mode Core B boot mode.
239 * brief Boots the other core.
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| D | fsl_mu.h | 71 …kMU_ResetAssertInterruptFlag = MU_SR_RAIP_MASK, /*!< The other core reset assert interrupt pending…
74 …kMU_ResetDeassertInterruptFlag = MU_SR_RDIP_MASK, /*!< The other core reset de-assert interrupt pe…
110 kMU_ResetAssertInterruptEnable = MU_CR_RAIE_MASK, /*!< The other core reset assert interrupt. */
113 …kMU_ResetDeassertInterruptEnable = MU_CR_RDIE_MASK, /*!< The other core reset de-assert interrupt.…
127 * @brief MU interrupt that could be triggered to the other core.
482 * @brief Triggers interrupts to the other core.
484 * This function triggers the specific interrupts to the other core. The interrupts
486 * The MU should not trigger an interrupt to the other core when the previous interrupt
487 * has not been processed by the other core. This function checks whether the
494 * has not been processed by the other core.
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/mcx_spc/ |
| D | fsl_spc.h | 72 …kStatus_SPC_CORELDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 5U), /*!< CORE LDO Low d…
74 …kStatus_SPC_CORELDOVoltageWrong = MAKE_STATUS(kStatusGroup_SPC, 7U), /*!< Core LDO volta…
75 …kStatus_SPC_CORELDOVoltageSetFail = MAKE_STATUS(kStatusGroup_SPC, 8U), /*!< Core LDO volta…
91 …kSPC_CoreVDDHighVoltageDetectFlag = SPC_VD_STAT_COREVDD_HVDF_MASK, /*!< Core VDD High-Voltage det…
93 …kSPC_CoreVDDLowVoltageDetectFlag = SPC_VD_STAT_COREVDD_LVDF_MASK, /*!< Core VDD Low-Voltage dete…
237 * @brief Core LDO regulator voltage level enumeration in Active mode or Low Power mode.
243 …kSPC_Core_LDO_RetentionVoltage = 0x0U, /*!< Core LDO VDD regulator regulate to retention voltage, …
246 …kSPC_CoreLDO_MidDriveVoltage = 0x1U, /*!< Core LDO VDD regulator regulate to Mid Drive Voltage. …
247 … kSPC_CoreLDO_NormalVoltage = 0x2U, /*!< Core LDO VDD regulator regulate to Normal Voltage. */
248 …kSPC_CoreLDO_OverDriveVoltage = 0x3U, /*!< Core LDO VDD regulator regulate to overdrive Voltage. …
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| D | fsl_spc.c | 106 …* brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and…
307 * brief Configs CORE voltage detect options.
309 * This function configs CORE voltage detect options.
335 * brief Enables the Core High Voltage Detector in Active mode.
341 * param enable Enable/Disable Core HVD.
342 * true - Enable Core High voltage detector in active mode.
343 * false - Disable Core High voltage detector in active mode.
345 * retval kStatus_Success Enable Core High Voltage Detect successfully.
364 * brief Enables the Core High Voltage Detector in Low Power mode.
371 * param enable Enable/Disable Core HVD.
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/spc/ |
| D | fsl_spc.h | 51 …kStatusGroup_SPC, 5U), /*!< CORE LDO Low driver strength setting be ignored for LDO LVD/HVD enable…
52 …kStatus_SPC_CORELDOVoltageWrong = MAKE_STATUS(kStatusGroup_SPC, 7U), /*!< Core LDO voltage is wr…
53 …kStatus_SPC_CORELDOVoltageSetFail = MAKE_STATUS(kStatusGroup_SPC, 8U), /*!< Core LDO voltage set f…
64 …kSPC_CoreVDDHighVoltageDetectFlag = SPC_VD_STAT_COREVDD_HVDF_MASK, /*!< Core VDD High-Voltage de…
67 …kSPC_CoreVDDLowVoltageDetectFlag = SPC_VD_STAT_COREVDD_LVDF_MASK, /*!< Core VDD Low-Voltage det…
185 * @brief Core LDO regulator voltage level enumeration in Active mode or Low Power mode.
190 … kSPC_CoreLDO_NormalVoltage = 0x0U, /*!< Core LDO VDD regulator regulate to Normal Voltage. */
191 …kSPC_CoreLDO_MidDriveVoltage = 0x1U, /*!< Core LDO VDD regulator regulate to Mid Drive Voltage. …
192 …kSPC_CoreLDO_UnderDriveVoltage = 0x2U, /*!< Core LDO VDD regulator regulate to Under Drive Voltage…
193 …kSPC_CoreLDO_SafeModeVoltage = 0x3U, /*!< Core LDO VDD regulator regulate to Safe-Mode Voltage. …
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| /hal_nxp-latest/mcux/middleware/mcux-sdk-middleware-multicore/mcmgr/src/ |
| D | mcmgr.h | 35 /*! @brief Enumeration that defines property of core. */
38 /*! @brief Status of core read from hardware core status flag. */
40 /*! @brief Type of Core. */
42 /*! @brief Power Mode of Core - implementation is hardware-specific. */
46 /*! @brief Enumeration that defines the property value of core status. */
49 /*! @brief Core is held in reset. */
51 /*! @brief Core is not in reset. */
55 /*! @brief Enumeration that defines property value of core type. */
72 /*! @brief Enumeration that defines core. */
75 /*! @brief Enum value for Core 0. */
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| D | mcmgr_internal_core_api.h | 27 /*! @brief Type definition of structure which contains informations and functions for one core. */
34 /*! @brief Type definition of possible core states. */
43 /*! @brief Type definition of structure which contains status information for a core. */
46 /*! @brief Current state of the core. */
59 /*! @brief Array of core informations. */
81 * This array contains runtime context for each core in the system.
89 * @param[in] coreNum Current core number.
98 * @param[in] coreNum Current core number.
105 * @brief Internal platform-specific start core function.
107 * @param[in] coreNum Enum of the core to be started.
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/mu1/ |
| D | fsl_mu.c | 203 /* Core interrupt. */ in MU_GetStatusFlags()
211 * brief Triggers interrupts to the other core.
213 * This function triggers the specific interrupts to the other core. The interrupts
215 * The MU should not trigger an interrupt to the other core when the previous interrupt
216 * has not been processed by the other core. This function checks whether the
223 * has not been processed by the other core.
240 * brief Triggers general purpose interrupts to the other core.
242 * This function triggers the specific general purpose interrupts to the other core.
244 * The MU should not trigger an interrupt to the other core when the previous interrupt
245 * has not been processed by the other core. This function checks whether the
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| D | fsl_mu.h | 78 …kMU_CoreEventPendingFlag = MU_STAT_FLAG(MU_SR_CEP_MASK), /*!< The other core mode entry event pend…
111 /*! The other core reset assert interrupt. */
162 /*! The other core reset assert interrupt. */
178 * @brief MU interrupt that could be triggered to the other core.
190 * @brief MU core status flags.
215 kMU_OtherSideEnterResetFlag = MU_CSSR0_RAIP_MASK, /*!< The other core entered reset. */
237 * @brief The other core boot mode.
535 * @brief Gets the MU core status flags.
614 /* Core interrupt. */ in MU_ClearStatusFlags()
672 /* Core interrupts. */ in MU_EnableInterrupts()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/ |
| D | fsl_soc_src.h | 87 * @brief System core.
91 kSRC_CM7Core = 0x1U, /*!< System Core CM4. */
92 kSRC_CM4Core = 0x2U, /*!< System Core CM7. */
112 kSRC_M4LockUpReset = 6U, /*!< M4 core lockup triggers the global system reset. */
113 kSRC_M7LockUpReset = 8U, /*!< M7 core lockup triggers the global system reset. */
114 kSRC_M4RequestReset = 10U, /*!< M4 core request triggers the global system reset. */
115 kSRC_M7RequestReset = 12U, /*!< M7 core request triggers the global system reset. */
127 …kSRC_M7CoreIppResetFlag = 1UL << 0UL, /*!< The M7 Core reset is the result of ipp_reset_b p…
128 …kSRC_M7CoreM7RequestResetFlag = 1UL << 1UL, /*!< The M7 Core reset is the result of M7 core reset…
129 …kSRC_M7CoreM7LockUpResetFlag = 1UL << 2UL, /*!< The M7 Core reset is the result of M7 core lock …
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/ |
| D | fsl_soc_src.h | 87 * @brief System core.
91 kSRC_CM7Core = 0x1U, /*!< System Core CM4. */
92 kSRC_CM4Core = 0x2U, /*!< System Core CM7. */
112 kSRC_M4LockUpReset = 6U, /*!< M4 core lockup triggers the global system reset. */
113 kSRC_M7LockUpReset = 8U, /*!< M7 core lockup triggers the global system reset. */
114 kSRC_M4RequestReset = 10U, /*!< M4 core request triggers the global system reset. */
115 kSRC_M7RequestReset = 12U, /*!< M7 core request triggers the global system reset. */
127 …kSRC_M7CoreIppResetFlag = 1UL << 0UL, /*!< The M7 Core reset is the result of ipp_reset_b p…
128 …kSRC_M7CoreM7RequestResetFlag = 1UL << 1UL, /*!< The M7 Core reset is the result of M7 core reset…
129 …kSRC_M7CoreM7LockUpResetFlag = 1UL << 2UL, /*!< The M7 Core reset is the result of M7 core lock …
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/ |
| D | fsl_soc_src.h | 87 * @brief System core.
91 kSRC_CM7Core = 0x1U, /*!< System Core CM4. */
92 kSRC_CM4Core = 0x2U, /*!< System Core CM7. */
112 kSRC_M4LockUpReset = 6U, /*!< M4 core lockup triggers the global system reset. */
113 kSRC_M7LockUpReset = 8U, /*!< M7 core lockup triggers the global system reset. */
114 kSRC_M4RequestReset = 10U, /*!< M4 core request triggers the global system reset. */
115 kSRC_M7RequestReset = 12U, /*!< M7 core request triggers the global system reset. */
127 …kSRC_M7CoreIppResetFlag = 1UL << 0UL, /*!< The M7 Core reset is the result of ipp_reset_b p…
128 …kSRC_M7CoreM7RequestResetFlag = 1UL << 1UL, /*!< The M7 Core reset is the result of M7 core reset…
129 …kSRC_M7CoreM7LockUpResetFlag = 1UL << 2UL, /*!< The M7 Core reset is the result of M7 core lock …
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/ |
| D | fsl_soc_src.h | 87 * @brief System core.
91 kSRC_CM7Core = 0x1U, /*!< System Core CM4. */
92 kSRC_CM4Core = 0x2U, /*!< System Core CM7. */
112 kSRC_M4LockUpReset = 6U, /*!< M4 core lockup triggers the global system reset. */
113 kSRC_M7LockUpReset = 8U, /*!< M7 core lockup triggers the global system reset. */
114 kSRC_M4RequestReset = 10U, /*!< M4 core request triggers the global system reset. */
115 kSRC_M7RequestReset = 12U, /*!< M7 core request triggers the global system reset. */
127 …kSRC_M7CoreIppResetFlag = 1UL << 0UL, /*!< The M7 Core reset is the result of ipp_reset_b p…
128 …kSRC_M7CoreM7RequestResetFlag = 1UL << 1UL, /*!< The M7 Core reset is the result of M7 core reset…
129 …kSRC_M7CoreM7LockUpResetFlag = 1UL << 2UL, /*!< The M7 Core reset is the result of M7 core lock …
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/ |
| D | fsl_soc_src.h | 87 * @brief System core.
91 kSRC_CM7Core = 0x1U, /*!< System Core CM4. */
92 kSRC_CM4Core = 0x2U, /*!< System Core CM7. */
112 kSRC_M4LockUpReset = 6U, /*!< M4 core lockup triggers the global system reset. */
113 kSRC_M7LockUpReset = 8U, /*!< M7 core lockup triggers the global system reset. */
114 kSRC_M4RequestReset = 10U, /*!< M4 core request triggers the global system reset. */
115 kSRC_M7RequestReset = 12U, /*!< M7 core request triggers the global system reset. */
127 …kSRC_M7CoreIppResetFlag = 1UL << 0UL, /*!< The M7 Core reset is the result of ipp_reset_b p…
128 …kSRC_M7CoreM7RequestResetFlag = 1UL << 1UL, /*!< The M7 Core reset is the result of M7 core reset…
129 …kSRC_M7CoreM7LockUpResetFlag = 1UL << 2UL, /*!< The M7 Core reset is the result of M7 core lock …
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/ |
| D | fsl_soc_src.h | 87 * @brief System core.
91 kSRC_CM7Core = 0x1U, /*!< System Core CM4. */
92 kSRC_CM4Core = 0x2U, /*!< System Core CM7. */
112 kSRC_M4LockUpReset = 6U, /*!< M4 core lockup triggers the global system reset. */
113 kSRC_M7LockUpReset = 8U, /*!< M7 core lockup triggers the global system reset. */
114 kSRC_M4RequestReset = 10U, /*!< M4 core request triggers the global system reset. */
115 kSRC_M7RequestReset = 12U, /*!< M7 core request triggers the global system reset. */
127 …kSRC_M7CoreIppResetFlag = 1UL << 0UL, /*!< The M7 Core reset is the result of ipp_reset_b p…
128 …kSRC_M7CoreM7RequestResetFlag = 1UL << 1UL, /*!< The M7 Core reset is the result of M7 core reset…
129 …kSRC_M7CoreM7LockUpResetFlag = 1UL << 2UL, /*!< The M7 Core reset is the result of M7 core lock …
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/ |
| D | fsl_soc_src.h | 87 * @brief System core.
91 kSRC_CM7Core = 0x1U, /*!< System Core CM4. */
92 kSRC_CM4Core = 0x2U, /*!< System Core CM7. */
112 kSRC_M4LockUpReset = 6U, /*!< M4 core lockup triggers the global system reset. */
113 kSRC_M7LockUpReset = 8U, /*!< M7 core lockup triggers the global system reset. */
114 kSRC_M4RequestReset = 10U, /*!< M4 core request triggers the global system reset. */
115 kSRC_M7RequestReset = 12U, /*!< M7 core request triggers the global system reset. */
127 …kSRC_M7CoreIppResetFlag = 1UL << 0UL, /*!< The M7 Core reset is the result of ipp_reset_b p…
128 …kSRC_M7CoreM7RequestResetFlag = 1UL << 1UL, /*!< The M7 Core reset is the result of M7 core reset…
129 …kSRC_M7CoreM7LockUpResetFlag = 1UL << 2UL, /*!< The M7 Core reset is the result of M7 core lock …
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/ |
| D | fsl_dcdc.h | 50 * @brief CORE slice.
54 kDCDC_CORE0 = 0x0U, /*!< CORE slice 0. */
55 kDCDC_CORE1 = 0x1U, /*!< CORE slice 1. */
332 dcdc_core_slice_t core, in DCDC_SetVDD1P0LowPowerModeTargetVoltage() argument
337 if (core == kDCDC_CORE0) in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
342 else if (core == kDCDC_CORE1) in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
383 static inline void DCDC_EnableVDD1P0LowPowerMode(DCDC_Type *base, dcdc_core_slice_t core, bool enab… in DCDC_EnableVDD1P0LowPowerMode() argument
385 if (core == kDCDC_CORE0) in DCDC_EnableVDD1P0LowPowerMode()
389 else if (core == kDCDC_CORE1) in DCDC_EnableVDD1P0LowPowerMode()
403 * @param core Core for DCDC to control.
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/ |
| D | fsl_dcdc.h | 50 * @brief CORE slice.
54 kDCDC_CORE0 = 0x0U, /*!< CORE slice 0. */
55 kDCDC_CORE1 = 0x1U, /*!< CORE slice 1. */
332 dcdc_core_slice_t core, in DCDC_SetVDD1P0LowPowerModeTargetVoltage() argument
337 if (core == kDCDC_CORE0) in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
342 else if (core == kDCDC_CORE1) in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
383 static inline void DCDC_EnableVDD1P0LowPowerMode(DCDC_Type *base, dcdc_core_slice_t core, bool enab… in DCDC_EnableVDD1P0LowPowerMode() argument
385 if (core == kDCDC_CORE0) in DCDC_EnableVDD1P0LowPowerMode()
389 else if (core == kDCDC_CORE1) in DCDC_EnableVDD1P0LowPowerMode()
403 * @param core Core for DCDC to control.
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/ |
| D | fsl_dcdc.h | 50 * @brief CORE slice.
54 kDCDC_CORE0 = 0x0U, /*!< CORE slice 0. */
55 kDCDC_CORE1 = 0x1U, /*!< CORE slice 1. */
332 dcdc_core_slice_t core, in DCDC_SetVDD1P0LowPowerModeTargetVoltage() argument
337 if (core == kDCDC_CORE0) in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
342 else if (core == kDCDC_CORE1) in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
383 static inline void DCDC_EnableVDD1P0LowPowerMode(DCDC_Type *base, dcdc_core_slice_t core, bool enab… in DCDC_EnableVDD1P0LowPowerMode() argument
385 if (core == kDCDC_CORE0) in DCDC_EnableVDD1P0LowPowerMode()
389 else if (core == kDCDC_CORE1) in DCDC_EnableVDD1P0LowPowerMode()
403 * @param core Core for DCDC to control.
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/ |
| D | fsl_dcdc.h | 50 * @brief CORE slice.
54 kDCDC_CORE0 = 0x0U, /*!< CORE slice 0. */
55 kDCDC_CORE1 = 0x1U, /*!< CORE slice 1. */
332 dcdc_core_slice_t core, in DCDC_SetVDD1P0LowPowerModeTargetVoltage() argument
337 if (core == kDCDC_CORE0) in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
342 else if (core == kDCDC_CORE1) in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
383 static inline void DCDC_EnableVDD1P0LowPowerMode(DCDC_Type *base, dcdc_core_slice_t core, bool enab… in DCDC_EnableVDD1P0LowPowerMode() argument
385 if (core == kDCDC_CORE0) in DCDC_EnableVDD1P0LowPowerMode()
389 else if (core == kDCDC_CORE1) in DCDC_EnableVDD1P0LowPowerMode()
403 * @param core Core for DCDC to control.
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