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/Zephyr-Core-3.4.0/samples/shields/npm6001_ek/doc/
Dindex.rst122 # configure GPIO 0 as output
123 npm6001 gpio configure -p 0 -d out
124 # configure GPIO 0 as output (init high)
125 npm6001 gpio configure -p 0 -d outh
126 # configure GPIO 0 as output (init low)
127 npm6001 gpio configure -p 0 -d outl
128 # configure GPIO 0 as output with high-drive mode enabled
129 npm6001 gpio configure -p 0 -d out --high-drive
130 # configure GPIO 1 as input
131 npm6001 gpio configure -p 1 -d input
[all …]
/Zephyr-Core-3.4.0/drivers/serial/
DKconfig.stellaris21 This tells the driver to configure the UART port at boot, depending on
22 the additional configure options below.
29 This tells the driver to configure the UART port at boot, depending on
30 the additional configure options below.
37 This tells the driver to configure the UART port at boot, depending on
38 the additional configure options below.
DKconfig.sifive21 This tells the driver to configure the UART port at boot, depending on
22 the additional configure options below.
44 This tells the driver to configure the UART port at boot, depending on
45 the additional configure options below.
/Zephyr-Core-3.4.0/boards/arc/hsdk/support/
Dopenocd.cfg5 # Configure JTAG cable
58 $_TARGETNAME2 configure -coreid $_coreid
59 $_TARGETNAME2 configure -dbgbase $_dbgbase
60 $_TARGETNAME2 configure -event reset-assert "arc_common_reset $_TARGETNAME2"
73 $_TARGETNAME3 configure -coreid $_coreid
74 $_TARGETNAME3 configure -dbgbase $_dbgbase
75 $_TARGETNAME3 configure -event reset-assert "arc_common_reset $_TARGETNAME3"
88 $_TARGETNAME4 configure -coreid $_coreid
89 $_TARGETNAME4 configure -dbgbase $_dbgbase
91 $_TARGETNAME4 configure -event reset-assert "arc_hs_reset $_TARGETNAME4"
[all …]
Dopenocd-2-cores.cfg5 # Configure JTAG cable
58 $_TARGETNAME2 configure -coreid $_coreid
59 $_TARGETNAME2 configure -dbgbase $_dbgbase
60 $_TARGETNAME2 configure -event reset-assert "arc_common_reset $_TARGETNAME2"
73 $_TARGETNAME1 configure -coreid $_coreid
74 $_TARGETNAME1 configure -dbgbase $_dbgbase
75 $_TARGETNAME1 configure -event reset-assert "arc_common_reset $_TARGETNAME1"
/Zephyr-Core-3.4.0/boards/arc/hsdk4xd/support/
Dopenocd.cfg5 # Configure JTAG cable
58 $_TARGETNAME2 configure -coreid $_coreid
59 $_TARGETNAME2 configure -dbgbase $_dbgbase
60 $_TARGETNAME2 configure -event reset-assert "arc_common_reset $_TARGETNAME2"
73 $_TARGETNAME3 configure -coreid $_coreid
74 $_TARGETNAME3 configure -dbgbase $_dbgbase
75 $_TARGETNAME3 configure -event reset-assert "arc_common_reset $_TARGETNAME3"
88 $_TARGETNAME4 configure -coreid $_coreid
89 $_TARGETNAME4 configure -dbgbase $_dbgbase
91 $_TARGETNAME4 configure -event reset-assert "arc_hs_reset $_TARGETNAME4"
[all …]
/Zephyr-Core-3.4.0/tests/drivers/uart/uart_basic_api/src/
Dtest_uart_config.c11 * @brief TestPurpose: verify UART configure API settings
14 * - Configure: test_uart_configure( )
15 * - Configure Get: test_uart_config_get( )
17 * -# When test UART CONFIG Configure, the value of configurations actually
21 * -# When test UART CONFIG Configure Get, the app will get/retrieve the
23 * CONFIG Configure
46 /* Verify configure() - set device configuration using data in cfg */ in test_configure()
58 /* test UART configure get (retrieve configuration) */
70 /* Verify configure() - set device configuration using data in cfg */ in test_config_get()
/Zephyr-Core-3.4.0/soc/arm/rpi_pico/rp2/
DKconfig.soc25 Configure RP2 to use a W25Q080 flash chip, or similar. Should be selected
31 Configure RP2 to use a flash chip supporting the standard 03h command.
37 Configure RP2 to use a IS25LP080 flash chip, or similar. Should be selected
43 Configure RP2 to use a W25X10CL flash chip, or similar. Should be selected
49 Configure RP2 to use a AT25SF128A flash chip, or similar. Should be selected
/Zephyr-Core-3.4.0/drivers/sensor/mchp_tach_xec/
DKconfig26 bool "Configure 9 tach edges or 4 tach periods"
29 bool "Configure 5 tach edges or 2 tach periods"
32 bool "Configure 3 tach edges or 1 tach period"
35 bool "Configure 2 tach edges or 1/2 tach period"
/Zephyr-Core-3.4.0/soc/arm/atmel_sam/common/
Dsoc_gpio.c29 /* Configure pull-up(s) */ in configure_common_attr()
36 /* Configure pull-down only for MCU series that support it */ in configure_common_attr()
38 /* Configure pull-down(s) */ in configure_common_attr()
46 /* Configure open drain (multi-drive) */ in configure_common_attr()
56 /* Configure input filter */ in configure_input_attr()
78 /* Configure interrupt */ in configure_input_attr()
84 /* Configure additional interrupt mode */ in configure_input_attr()
124 /* Configure pin attributes common to all functions */ in soc_gpio_configure()
169 /* Configure pin attributes related to input function */ in soc_gpio_configure()
171 /* Configure pin as input */ in soc_gpio_configure()
[all …]
/Zephyr-Core-3.4.0/boards/arm/stm32f746g_disco/support/
Dopenocd.cfg3 $_TARGETNAME configure -event gdb-attach {
9 $_TARGETNAME configure -event gdb-detach {
17 $_TARGETNAME configure -event reset-start {
/Zephyr-Core-3.4.0/boards/arm/stm32f7508_dk/support/
Dopenocd.cfg3 $_TARGETNAME configure -event gdb-attach {
9 $_TARGETNAME configure -event gdb-detach {
17 $_TARGETNAME configure -event reset-start {
/Zephyr-Core-3.4.0/boards/arm/efm32gg_slwstk6121a/support/
Dopenocd.cfg16 $_TARGETNAME configure -event gdb-attach {
22 $_TARGETNAME configure -event gdb-detach {
27 $_TARGETNAME configure -rtos auto
/Zephyr-Core-3.4.0/boards/arm/efm32gg_stk3701a/support/
Dopenocd.cfg16 $_TARGETNAME configure -event gdb-attach {
22 $_TARGETNAME configure -event gdb-detach {
27 $_TARGETNAME configure -rtos auto
/Zephyr-Core-3.4.0/subsys/net/l2/ppp/
DKconfig23 int "Maximum timeout in ms for Configure-Req"
27 How long to wait Configure-Req.
30 int "Maximum number of Configure-Req retransmits"
34 How many times to resend Configure-Req messages before deciding the
94 configure at run-time ppp drivers and L2 settings.
/Zephyr-Core-3.4.0/tests/drivers/gpio/gpio_api_1pin/src/
Dtest_pin_interrupt.c69 zassert_equal(ret, 0, "Failed to configure the pin"); in test_gpio_pin_interrupt_edge()
78 zassert_equal(ret, 0, "Failed to configure the pin"); in test_gpio_pin_interrupt_edge()
92 zassert_equal(ret, 0, "Failed to configure pin interrupt"); in test_gpio_pin_interrupt_edge()
143 zassert_equal(ret, 0, "Failed to configure the pin"); in test_gpio_pin_interrupt_level()
157 zassert_equal(ret, 0, "Failed to configure the pin"); in test_gpio_pin_interrupt_level()
172 zassert_equal(ret, 0, "Failed to configure pin interrupt"); in test_gpio_pin_interrupt_level()
229 TC_PRINT("Step 1: Configure pin as active high\n"); in ZTEST()
231 TC_PRINT("Step 2: Configure pin as active low\n"); in ZTEST()
238 TC_PRINT("Step 1: Configure pin as active high\n"); in ZTEST()
240 TC_PRINT("Step 2: Configure pin as active low\n"); in ZTEST()
[all …]
/Zephyr-Core-3.4.0/boards/arm/cc3235sf_launchxl/
Dpinmux.c10 * configure the device pins for different peripheral signals
71 /* Configure PIN_55 for UART0 UART0_TX */ in pinmux_initialize()
74 /* Configure PIN_57 for UART0 UART0_RX */ in pinmux_initialize()
83 /* Configure PIN_64 for GPIOOutput */ in pinmux_initialize()
87 /* Configure PIN_01 for GPIOOutput */ in pinmux_initialize()
91 /* Configure PIN_02 for GPIOOutput */ in pinmux_initialize()
95 /* SW3: Configure PIN_04 (GPIO13) for GPIOInput */ in pinmux_initialize()
101 /* SW2: Configure PIN_15 (GPIO22) for GPIOInput */ in pinmux_initialize()
/Zephyr-Core-3.4.0/arch/arm/core/aarch32/mpu/
Darm_core_mpu_dev.h53 * @brief Maximum number of MPU regions required to configure a
74 * @brief Maximum number of MPU regions required to configure a
112 * @brief configure a set of fixed (static) MPU regions
114 * Internal API function to configure a set of static MPU memory regions,
149 * Internal API function to configure a set of memory regions, determined
173 * @brief configure a set of dynamic MPU regions
175 * Internal API function to configure a set of dynamic MPU memory regions
195 * Internal API function to re-configure the access permissions of an
213 * @brief configure the base address and size for an MPU region
222 * @brief configure MPU regions for the memory partitions of the memory domain
[all …]
/Zephyr-Core-3.4.0/soc/arm/cypress/psoc6/
Dsoc.c124 /* Configure power mode */ in init_cycfg_platform()
130 /* Configure PMIC */ in init_cycfg_platform()
163 /* Configure CPU clock dividers */ in init_cycfg_platform()
176 /* Configure HF clocks */ in init_cycfg_platform()
226 /* Configure Path Clocks */ in init_cycfg_platform()
276 /* Configure and enable FLL */ in init_cycfg_platform()
281 /* Configure and enable PLLs */ in init_cycfg_platform()
328 /* Configure miscellaneous clocks */ in init_cycfg_platform()
345 /* Configure default enabled clocks */ in init_cycfg_platform()
374 /* Configure platform resources */ in Cy_SystemInit()
[all …]
/Zephyr-Core-3.4.0/arch/arc/core/mpu/
Darc_mpu_common_internal.h18 * @brief configure the base address and size for an MPU region
67 * @brief configure the thread's MPU regions
74 /* configure stack region of user thread */ in arc_core_mpu_configure_thread()
76 LOG_DBG("configure user thread %p's stack", thread); in arc_core_mpu_configure_thread()
85 LOG_DBG("configure thread %p's domain", thread); in arc_core_mpu_configure_thread()
92 * @brief configure the default region
105 * @brief configure the MPU region
127 * @brief configure MPU regions for the memory partitions of the memory domain
143 LOG_DBG("configure domain: %p", mem_domain); in arc_core_mpu_configure_mem_domain()
247 __ASSERT(0, "Request to configure: %u regions (supported: %u)\n", in arc_mpu_init()
[all …]
/Zephyr-Core-3.4.0/soc/arm/cypress/common/
Dsoc_gpio.h74 * @brief Configure GPIO pin(s).
76 * Configure one or several pins belonging to the same GPIO port.
78 * - configure pin(s) as input with debounce filter enabled.
80 * - configure pin(s) as open drain output.
88 * @brief Configure a list of GPIO pin(s).
90 * Configure an arbitrary amount of pins in an arbitrary way. Each
/Zephyr-Core-3.4.0/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/
Dradio_df.h30 /* Configure CTE transmission with 2us antenna switching for AoD. */
32 /* Configure CTE transmission with 4us antenna switching for AoD. */
34 /* Configure CTE transmission with for AoA. */
36 /* Configure CTE reception with optionall AoA mode and 2us antenna switching. */
38 /* Configure CTE reception with optionall AoA mode and 4us antenna switching. */
/Zephyr-Core-3.4.0/boards/riscv/hifive1/support/
Dopenocd.cfg14 $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
35 $_TARGETNAME configure -event gdb-attach {
40 $_TARGETNAME configure -event gdb-detach {
/Zephyr-Core-3.4.0/soc/arm/arm/beetle/
Dpower.c69 /* Configure AHB Peripheral Clock in active state */ in clock_active_init()
72 /* Configure APB Peripheral Clock in active state */ in clock_active_init()
83 /* Configure APB Peripheral Clock in sleep state */ in clock_sleep_init()
94 /* Configure APB Peripheral Clock in deep sleep state */ in clock_deepsleep_init()
106 /* Configure Wakeup Sources */ in wakeup_src_init()
/Zephyr-Core-3.4.0/drivers/pinctrl/
Dpinctrl_npcx.c120 /* Configure peripheral device's pinmux functionality */ in npcx_periph_configure()
125 /* Configure peripheral device's internal PU/PD */ in npcx_periph_configure()
129 /* Configure peripheral device's drive mode. (Only PWM pads support it) */ in npcx_periph_configure()
141 /* Configure detection polarity of PSL input pads */ in npcx_psl_input_detection_configure()
148 /* Configure detection mode of PSL input pads */ in npcx_psl_input_detection_configure()
162 /* Configure all peripheral devices' properties here. */ in pinctrl_configure_pins()
165 /* Configure peripheral device's pinmux functionality */ in pinctrl_configure_pins()
168 /* Configure SPL input's detection mode */ in pinctrl_configure_pins()

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