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/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/
Dclear_msi.overlay8 * Warning: This overlay clears the msi clock back to a state equivalent to what could
Dclear_f0_f1_f3_clocks.overlay8 * Warning: This overlay clears clocks back to a state equivalent to what could
Dclear_f2_f4_f7_clocks.overlay8 * Warning: This overlay clears clocks back to a state equivalent to what could
Dclear_clocks.overlay8 * Warning: This overlay clears clocks back to a state equivalent to what could
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/
Dadsp_watchdog.h24 * Clears the pause signal to resume the watchdog timing
Dadsp_ipc_regs.h47 * This clears BUSY on the other side of the connection in IDR register.
Dadsp_power.h66 * This clears the "not power gating" bit in the power control
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/
Dclear_clocks.overlay8 * Warning: This overlay clears clocks back to a state equivalent to what could
/Zephyr-latest/dts/bindings/watchdog/
Dti,tps382x.yaml16 TPS3823/4/8, TPS3823A. The timer clears when reset is asserted or
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/
Dclear_clocks.overlay8 * Warning: This overlay clears clocks back to a state equivalent to what could
/Zephyr-latest/drivers/flash/
Dsoc_flash_mcux.c133 /* this bit clears the flash cache */ in clear_flash_caches()
136 /* this bit clears the code cache */ in clear_flash_caches()
143 /* this bit clears the flash cache */ in clear_flash_caches()
146 /* this bit clears the code cache */ in clear_flash_caches()
/Zephyr-latest/subsys/demand_paging/eviction/
DKconfig50 A periodic timer will fire that clears the accessed state of all virtual
/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dcavstool.h31 /* The host clears the run bit and resets the HDA stream */
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/
Dclear_clocks.overlay9 * Warning: This overlay clears clocks back to a state equivalent to what could
/Zephyr-latest/include/zephyr/shell/
Dshell_dummy.h61 * @brief Clears the output buffer in the shell backend.
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/
Dclear_clocks.overlay8 * Warning: This overlay clears clocks back to a state equivalent to what could
/Zephyr-latest/drivers/interrupt_controller/
Dintc_nuclei_eclic.S34 * This function services and clears all pending interrupts for an ECLIC in non-vectored mode.
/Zephyr-latest/dts/bindings/regulator/
Dregulator-gpio.yaml69 array. The driver simply sets or clears the appropriate GPIO bit when
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dcore_init.overlay8 * Warning: This overlay clears clocks back to a state equivalent to what could
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/
Dadsp_ipc_regs.h47 * This clears BUSY on the other side of the connection in IDR register.
Dadsp_power.h67 * This clears the "not power gating" bit in the power control
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace30/
Dadsp_ipc_regs.h44 * This clears BUSY on the other side of the connection in IDR register.
/Zephyr-latest/samples/userspace/shared_mem/
DREADME.rst54 encrypted thread's private memory when the flag is set and then clears
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/
Dradio_df.h41 /* Clears antenna switch pattern. */
/Zephyr-latest/dts/bindings/pinctrl/
Dxlnx,pinctrl-zynq.yaml148 Disable any IO buffer pin bias. Clears the PULLUP and TRI_ENABLE fields in the MIO_PIN_xx
168 Enable HSTL input buffer. Applicable when the power-souce (IO_Type) is HSTL. Clears the

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