Searched full:chip (Results 1 – 25 of 933) sorted by relevance
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| /Zephyr-Core-3.5.0/tests/kernel/device/src/ |
| D | mmio_multireg.c | 20 DEVICE_MMIO_NAMED_RAM(chip);
27 DEVICE_MMIO_NAMED_ROM(chip);
32 DEVICE_MMIO_NAMED_ROM_INIT_BY_NAME(chip, DT_DRV_INST(0)),
41 DEVICE_MMIO_NAMED_MAP(dev, chip, K_MEM_CACHE_NONE); in foo_multireg_init()
69 regs_chip = DEVICE_MMIO_NAMED_GET(dev, chip); in ZTEST()
71 rom_chip = DEVICE_MMIO_NAMED_ROM_PTR(dev, chip); in ZTEST()
78 zassert_equal(rom_chip->phys_addr, DT_INST_REG_ADDR_BY_NAME(0, chip), in ZTEST()
79 "bad phys_addr (chip)"); in ZTEST()
80 zassert_equal(rom_chip->size, DT_INST_REG_SIZE_BY_NAME(0, chip), in ZTEST()
81 "bad size (chip)"); in ZTEST()
[all …]
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| /Zephyr-Core-3.5.0/dts/bindings/mtd/ |
| D | atmel,at45.yaml | 36 Value of zero means that the flash chip has all sectors of equal size.
48 no-chip-erase:
51 If set, indicates that the chip does not support the chip erase command.
56 If set, indicates that the chip does not support the sector erase command.
62 of the default Deep Power-Down one to put the chip into low power mode.
65 SRAM buffers in the chip, the difference between the Deep and Ultra-Deep
66 Power-Down modes is that the chip consumes far less power in the latter
73 Time, in nanoseconds, needed by the chip to enter the Deep Power-Down
81 Time, in nanoseconds, needed by the chip to exit from the Deep Power-Down
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| /Zephyr-Core-3.5.0/boards/arm/ev11l78a/doc/ |
| D | index.rst | 44 - on-chip
47 - on-chip
50 - on-chip
53 - on-chip
56 - on-chip
59 - on-chip
62 - on-chip
65 - on-chip
68 - on-chip
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| /Zephyr-Core-3.5.0/boards/arm/96b_carbon_nrf51/doc/ |
| D | index.rst | 9 This is the secondary nRF51822 chip on the 96Boards Carbon and provides
10 Bluetooth functionality to the main STM32F401RET chip via SPI.
16 unless they want to reprogram the secondary chip which provides
29 different chip.
37 | NVIC | on-chip | nested vector interrupt controller |
39 | RTC | on-chip | system clock |
41 | UART | on-chip | serial port |
43 | GPIO | on-chip | gpio |
45 | FLASH | on-chip | flash |
47 | SPIS | on-chip | SPI slave |
[all …]
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| /Zephyr-Core-3.5.0/soc/arm/rpi_pico/rp2/ |
| D | Kconfig.soc | 25 Configure RP2 to use a W25Q080 flash chip, or similar. Should be selected
31 Configure RP2 to use a flash chip supporting the standard 03h command.
37 Configure RP2 to use a IS25LP080 flash chip, or similar. Should be selected
43 Configure RP2 to use a W25X10CL flash chip, or similar. Should be selected
49 Configure RP2 to use a AT25SF128A flash chip, or similar. Should be selected
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| /Zephyr-Core-3.5.0/boards/arm/atsamc21n_xpro/doc/ |
| D | index.rst | 45 - on-chip
48 - on-chip
51 - on-chip
54 - on-chip
57 - on-chip
60 - on-chip
63 - on-chip
66 - on-chip
69 - on-chip
72 - on-chip
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/atsamd21_xpro/doc/ |
| D | index.rst | 46 - on-chip
49 - on-chip
52 - on-chip
55 - on-chip
58 - on-chip
61 - on-chip
64 - on-chip
67 - on-chip
70 - on-chip
73 - on-chip
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/atsamd20_xpro/doc/ |
| D | index.rst | 46 - on-chip
49 - on-chip
52 - on-chip
55 - on-chip
58 - on-chip
61 - on-chip
64 - on-chip
67 - on-chip
70 - on-chip
88 with the on-chip PLL generating the 48 MHz system clock.
[all …]
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| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | Kconfig.mcp23xxx | 13 bool "MCP230XX I2C-based GPIO chip"
19 Enable driver for MCP230XX I2C-based GPIO chip.
32 bool "MCP23SXX SPI-based GPIO chip"
38 Enable driver for MCP23SXX SPI-based GPIO chip.
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| /Zephyr-Core-3.5.0/boards/arm/atsaml21_xpro/doc/ |
| D | index.rst | 43 - on-chip
46 - on-chip
49 - on-chip
52 - on-chip
55 - on-chip
58 - on-chip
61 - on-chip
64 - on-chip
67 - on-chip
70 - on-chip
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/atsamr34_xpro/doc/ |
| D | index.rst | 48 - on-chip
51 - on-chip
54 - on-chip
57 - on-chip
60 - on-chip
63 - on-chip
66 - on-chip
69 - on-chip
72 - on-chip
75 - on-chip
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/wio_terminal/doc/ |
| D | index.rst | 53 - on-chip
56 - on-chip
59 - on-chip
62 - on-chip
65 - on-chip
68 - on-chip
71 - on-chip
74 - on-chip
77 - on-chip
80 - on-chip
[all …]
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| /Zephyr-Core-3.5.0/dts/bindings/spi/ |
| D | intel,penwell-spi.yaml | 22 Chip select configuration. possible values:
31 Use GSPI chip select CS0 or CS1. GSPI 0, 1 & 2 instance supports both chip selects.
33 Chip select output possible values:
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| D | microchip,xec-qmspi-ldma.yaml | 48 chip-select:
51 Use QMSPI CS0# or CS1#. Port 0 supports both chip selects.
58 If not present use hardware default value. Refer to chip documention
65 If not present use hardware default value. Refer to chip documention
72 and WP#. If not present use hardware default value. Refer to chip
79 If not present use hardware default value. Refer to chip documention
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| D | nxp,lpc-spi.yaml | 14 Delay in nanoseconds inserted between chip select assert to the first
20 Delay in nanoseconds inserted between the last clock edge to the chip
26 Delay in nanoseconds inserted between data frames when chip select is
33 Delay in nanoseconds inserted between transfers when chip select is
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| /Zephyr-Core-3.5.0/include/zephyr/devicetree/ |
| D | spi.h | 26 * @brief Does a SPI controller node have chip select GPIOs configured?
29 * chip select GPIOs. Its value is a phandle-array which specifies the
30 * chip select lines.
55 * @brief Number of chip select GPIOs in a SPI controller's cs-gpios property
83 * @brief Does a SPI device have a chip select line configured?
114 * @return 1 if spi_dev's bus node DT_BUS(spi_dev) has a chip select
120 * @brief Get a SPI device's chip select GPIO controller's node identifier
148 * @return node identifier for spi_dev's chip select GPIO controller
157 * @brief Get a SPI device's chip select GPIO controller's label property
189 * @return label property of spi_dev's chip select GPIO controller
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| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | richtek,rt1718s.yaml | 5 Richtek RT1718S TCPC chip
7 The Richtek RT1718S chip is TCPC, but also has 3 pins, which can be used as
8 a usual GPIO. This node collects common proprties for RT1718S chip e.g. I2C
36 description: Interrupt GPIO pin connected from the chip(IRQB)
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| /Zephyr-Core-3.5.0/boards/arm/sam_v71_xult/doc/ |
| D | index.rst | 49 | NVIC | on-chip | nested vector interrupt controller |
51 | SYSTICK | on-chip | systick |
53 | UART | on-chip | serial port |
55 | USART | on-chip | serial port |
57 | I2C | on-chip | i2c |
59 | SPI | on-chip | spi |
61 | ETHERNET | on-chip | ethernet |
63 | WATCHDOG | on-chip | watchdog |
65 | GPIO | on-chip | gpio |
67 | ADC | on-chip | ADC via AFEC |
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/sam_e70_xplained/doc/ |
| D | index.rst | 43 | NVIC | on-chip | nested vector interrupt controller |
45 | SYSTICK | on-chip | systick |
47 | UART | on-chip | serial port |
49 | USART | on-chip | serial port |
51 | I2C | on-chip | i2c |
53 | SPI | on-chip | spi |
55 | ETHERNET | on-chip | ethernet |
57 | WATCHDOG | on-chip | watchdog |
59 | GPIO | on-chip | gpio |
61 | ADC | on-chip | ADC via AFEC |
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/atsame54_xpro/doc/ |
| D | index.rst | 52 | ADC | on-chip | adc |
54 | DAC | on-chip | dac |
56 | DMAC | on-chip | dma |
60 | EIC | on-chip | interrupt_controller |
62 | GMAC | on-chip | ethernet, mdio |
64 | GPIO | on-chip | gpio |
66 | MPU | on-chip | arch/arm |
68 | NVIC | on-chip | arch/arm |
70 | NVMCTRL | on-chip | flash |
72 | PORT | on-chip | pinctrl |
[all …]
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| /Zephyr-Core-3.5.0/boards/riscv/it82xx2_evb/doc/ |
| D | index.rst | 22 The IT82XX2 series contains different chip types(ex, it82202, it82302),
53 - on-chip
56 - on-chip
59 - on-chip
62 - on-chip
65 - on-chip
68 - on-chip
71 - on-chip
74 - on-chip
77 - on-chip
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/rak4631_nrf52840/doc/ |
| D | index.rst | 48 | ADC | on-chip | adc |
50 | CLOCK | on-chip | clock_control |
52 | FLASH | on-chip | flash |
54 | GPIO | on-chip | gpio |
56 | I2C(M) | on-chip | i2c |
58 | MPU | on-chip | arch/arm |
60 | NVIC | on-chip | arch/arm |
62 | PWM | on-chip | pwm |
64 | RADIO | on-chip | Bluetooth, |
69 | RTC | on-chip | system clock |
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/rak5010_nrf52840/doc/ |
| D | index.rst | 56 | ADC | on-chip | adc |
58 | CLOCK | on-chip | clock_control |
60 | FLASH | on-chip | flash |
62 | GPIO | on-chip | gpio |
64 | I2C(M) | on-chip | i2c |
66 | MPU | on-chip | arch/arm |
68 | NVIC | on-chip | arch/arm |
70 | PWM | on-chip | pwm |
72 | RADIO | on-chip | Bluetooth, |
75 | RTC | on-chip | system clock |
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/adafruit_feather_nrf52840/doc/ |
| D | index.rst | 53 | ADC | on-chip | adc |
55 | CLOCK | on-chip | clock_control |
57 | FLASH | on-chip | flash |
59 | GPIO | on-chip | gpio |
61 | I2C | on-chip | i2c |
63 | MPU | on-chip | arch/arm |
65 | NVIC | on-chip | arch/arm |
67 | PWM | on-chip | pwm |
69 | RADIO | on-chip | Bluetooth, |
72 | RTC | on-chip | system clock |
[all …]
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| /Zephyr-Core-3.5.0/drivers/clock_control/ |
| D | Kconfig.npcx | 14 bool "Generate LFCLK by on-chip Crystal Oscillator"
18 is generated by the on-chip Crystal Oscillator (XTOSC).
19 This includes an on-chip oscillator, to which an external crystal
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