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/Zephyr-latest/dts/bindings/ethernet/
Dxlnx,gem.yaml25 clock control register in the CRL_APB. The GEM's TX clock frequency
/Zephyr-latest/drivers/ethernet/
Deth_xlnx_gem_priv.h132 * CRL_WPROT (CRL_APB) register:
135 * GEMx_REF_CTRL (CRL_APB) registers:
Deth_xlnx_gem.c845 * ZynqMP register crl_apb.GEMx_REF_CTRL: in eth_xlnx_gem_configure_clocks()
849 * Unlock CRL_APB write access if the write protect bit in eth_xlnx_gem_configure_clocks()
865 * Unlock CRL_APB write access if the write protect bit in eth_xlnx_gem_configure_clocks()