| /Zephyr-Core-3.5.0/boards/arc/nsim/ |
| D | nsim_hs5x_smp_12cores.dts | 20 cpu@0 {
21 device_type = "cpu";
26 cpu@1 {
27 device_type = "cpu";
32 cpu@2 {
33 device_type = "cpu";
38 cpu@3 {
39 device_type = "cpu";
44 cpu@4 {
45 device_type = "cpu";
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| D | nsim_hs6x_smp_12cores.dts | 20 cpu@0 {
21 device_type = "cpu";
26 cpu@1 {
27 device_type = "cpu";
32 cpu@2 {
33 device_type = "cpu";
38 cpu@3 {
39 device_type = "cpu";
44 cpu@4 {
45 device_type = "cpu";
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| /Zephyr-Core-3.5.0/doc/services/debugging/ |
| D | thread-analyzer.rst | 29 thread_a: Hello World from cpu 0 on qemu_x86!
31 thread_b : STACK: unused 740 usage 284 / 1024 (27 %); CPU: 0 %
32 thread_analyzer : STACK: unused 8 usage 504 / 512 (98 %); CPU: 0 %
33 thread_a : STACK: unused 648 usage 376 / 1024 (36 %); CPU: 98 %
34 idle : STACK: unused 204 usage 116 / 320 (36 %); CPU: 0 %
35 thread_b: Hello World from cpu 0 on qemu_x86!
36 thread_a: Hello World from cpu 0 on qemu_x86!
37 thread_b: Hello World from cpu 0 on qemu_x86!
38 thread_a: Hello World from cpu 0 on qemu_x86!
39 thread_b: Hello World from cpu 0 on qemu_x86!
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| /Zephyr-Core-3.5.0/kernel/ |
| D | usage.c | 36 static void sched_cpu_update_usage(struct _cpu *cpu, uint32_t cycles) in sched_cpu_update_usage() argument
38 if (!cpu->usage->track_usage) { in sched_cpu_update_usage()
42 if (cpu->current != cpu->idle_thread) { in sched_cpu_update_usage()
43 cpu->usage->total += cycles; in sched_cpu_update_usage()
46 cpu->usage->current += cycles; in sched_cpu_update_usage()
48 if (cpu->usage->longest < cpu->usage->current) { in sched_cpu_update_usage()
49 cpu->usage->longest = cpu->usage->current; in sched_cpu_update_usage()
52 cpu->usage->current = 0; in sched_cpu_update_usage()
53 cpu->usage->num_windows++; in sched_cpu_update_usage()
58 #define sched_cpu_update_usage(cpu, cycles) do { } while (0) argument
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| /Zephyr-Core-3.5.0/boards/arc/qemu_arc/ |
| D | board.cmake | 7 set(QEMU_FLAGS_${ARCH} -cpu arcem)
10 set(QEMU_FLAGS_${ARCH} -cpu archs)
14 set(QEMU_FLAGS_${ARCH} -cpu hs5x)
18 set(QEMU_FLAGS_${ARCH} -cpu hs6x)
33 -global cpu.firq=false
34 -global cpu.num-irqlevels=15
35 -global cpu.num-irq=25
36 -global cpu.ext-irq=20
37 -global cpu.freq_hz=10000000
38 -global cpu.timer0=true
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| /Zephyr-Core-3.5.0/dts/riscv/ |
| D | virt.dtsi | 41 cpu@0 {
42 device_type = "cpu";
48 compatible = "riscv,cpu-intc";
55 cpu@1 {
56 device_type = "cpu";
62 compatible = "riscv,cpu-intc";
69 cpu@2 {
70 device_type = "cpu";
76 compatible = "riscv,cpu-intc";
83 cpu@3 {
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| /Zephyr-Core-3.5.0/tests/boards/intel_adsp/smoke/src/ |
| D | cpus.c | 44 static void run_on_cpu(int cpu, void (*fn)(void *), void *arg, bool wait) in run_on_cpu() argument
46 __ASSERT_NO_MSG(cpu < arch_num_cpus()); in run_on_cpu()
52 k_thread_create(&run_on_threads[cpu], run_on_stacks[cpu], RUN_ON_STACKSZ, in run_on_cpu()
53 run_on_cpu_threadfn, fn, arg, (void *)&run_on_flags[cpu], in run_on_cpu()
55 k_thread_cpu_mask_clear(&run_on_threads[cpu]); in run_on_cpu()
56 k_thread_cpu_mask_enable(&run_on_threads[cpu], cpu); in run_on_cpu()
57 run_on_flags[cpu] = false; in run_on_cpu()
58 k_thread_start(&run_on_threads[cpu]); in run_on_cpu()
61 while (!run_on_flags[cpu]) { in run_on_cpu()
65 k_thread_abort(&run_on_threads[cpu]); in run_on_cpu()
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| D | smpboot.c | 9 /* Experimentally 10ms is enough time to get the second CPU to run on
14 /* IPIs happen much faster than CPU startup */
35 "running on wrong cpu"); in thread_fn()
51 printk("Launch cpu%d\n", i); in ZTEST()
60 /* Make sure that thread has not run (because the cpu is halted) */ in ZTEST()
62 zassert_false(mp_flag, "cpu %d must not be running yet", i); in ZTEST()
64 /* Start the second CPU */ in ZTEST()
69 zassert_true(mp_flag, "cpu %d did not start", i); in ZTEST()
83 * another CPU as soon as its created. Intended to test in ZTEST()
85 * CPU. in ZTEST()
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/common/include/ |
| D | soc.h | 24 extern void soc_mp_startup(uint32_t cpu);
34 * @brief Halts and offlines a running CPU
36 * Enables power gating on the specified CPU, which cannot be the
37 * current CPU or CPU 0. The CPU must be idle; no application threads
39 * CPU must be guaranteed to reach idle in finite time without
40 * deadlock). Actual CPU shutdown can only happen in the context of
42 * responsibility. This function will hang if the other CPU fails to
50 * @param id CPU to halt, not current cpu or cpu 0
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| /Zephyr-Core-3.5.0/subsys/pm/ |
| D | state.c | 15 * Check CPU power state consistency.
18 * @param node_id CPU node identifier.
26 "Found CPU power state with min_residency < exit_latency")
29 * @brief Check CPU power states consistency
33 * @param node_id A CPU node identifier.
49 /** CPU power states information for each CPU */
54 /** Number of states for each CPU */
59 uint8_t pm_state_cpu_get_all(uint8_t cpu, const struct pm_state_info **states) in pm_state_cpu_get_all() argument
61 if (cpu >= ARRAY_SIZE(cpus_states)) { in pm_state_cpu_get_all()
65 *states = cpus_states[cpu]; in pm_state_cpu_get_all()
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| /Zephyr-Core-3.5.0/boards/riscv/qemu_riscv32e/doc/ |
| D | index.rst | 37 thread_a: Hello World from cpu 0 on qemu_riscv32e!
38 thread_b: Hello World from cpu 0 on qemu_riscv32e!
39 thread_a: Hello World from cpu 0 on qemu_riscv32e!
40 thread_b: Hello World from cpu 0 on qemu_riscv32e!
41 thread_a: Hello World from cpu 0 on qemu_riscv32e!
42 thread_b: Hello World from cpu 0 on qemu_riscv32e!
43 thread_a: Hello World from cpu 0 on qemu_riscv32e!
44 thread_b: Hello World from cpu 0 on qemu_riscv32e!
45 thread_a: Hello World from cpu 0 on qemu_riscv32e!
46 thread_b: Hello World from cpu 0 on qemu_riscv32e!
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/ |
| D | adsp_power.h | 50 * @brief Power up a specific CPU.
53 * register to disable power gating to CPU, thus powering up
54 * the CPU.
56 * @param cpu_num CPU to be powered up.
64 * @brief Power down a specific CPU.
67 * register to enable power gating to CPU, thus powering down
68 * the CPU.
70 * @param cpu_num CPU to be powered down.
78 * @brief Test if a CPU is currently powered.
80 * This queries the power status register to see if the CPU
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/ |
| D | adsp_power.h | 50 * @brief Power up a specific CPU.
53 * register to disable power gating to CPU, thus powering up
54 * the CPU.
56 * @param cpu_num CPU to be powered up.
64 * @brief Power down a specific CPU.
67 * register to enable power gating to CPU, thus powering down
68 * the CPU.
70 * @param cpu_num CPU to be powered down.
78 * @brief Test if a CPU is currently powered.
80 * This queries the power status register to see if the CPU
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| /Zephyr-Core-3.5.0/dts/arm64/rockchip/ |
| D | rk3399.dtsi | 19 cpu@0 {
20 device_type = "cpu";
24 cpu@1 {
25 device_type = "cpu";
29 cpu@2 {
30 device_type = "cpu";
34 cpu@3 {
35 device_type = "cpu";
39 cpu@4 {
40 device_type = "cpu";
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| /Zephyr-Core-3.5.0/samples/drivers/ipm/ipm_mhu_dual_core/ |
| D | README.rst | 14 1. CPU 0 will wake up CPU 1 after initialization
15 2. CPU 1 will send to CPU 0 an interrupt over MHU0
16 3. CPU 0 return the same to CPU 1 when received MHU0 interrupt
17 4. Test done when CPU 1 received MHU0 interrupt
26 It can be built and executed on Musca B1 CPU 0 as follows:
35 It can be built and executed on Musca B1 CPU 1 as follows:
74 CPU 0, get MHU0 success!
77 CPU 1, get MHU0 success!
78 MHU ISR on CPU 0
79 MHU ISR on CPU 1
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| /Zephyr-Core-3.5.0/dts/arm64/ti/ |
| D | ti_am6234_a53.dtsi | 14 cpu@1 {
15 device_type = "cpu";
20 cpu@2 {
21 device_type = "cpu";
26 cpu@3 {
27 device_type = "cpu";
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| /Zephyr-Core-3.5.0/drivers/interrupt_controller/ |
| D | intc_esp32.c | 78 printk("Unhandled interrupt %d on cpu %d!\n", (int)arg, esp_core_id()); in default_intr_handler()
91 /* Linked list of vector descriptions, sorted by cpu.intno value */
102 * with an incrementing cpu.intno value.
110 if (vd->cpu > to_insert->cpu) { in insert_vector_desc()
113 if (vd->cpu == to_insert->cpu && vd->intno >= to_insert->intno) { in insert_vector_desc()
129 /* Returns a vector_desc entry for an intno/cpu, or NULL if none exists. */
130 static struct vector_desc_t *find_desc_for_int(int intno, int cpu) in find_desc_for_int() argument
135 if (vd->cpu == cpu && vd->intno == intno) { in find_desc_for_int()
144 * Returns a vector_desc entry for an intno/cpu.
148 static struct vector_desc_t *get_desc_for_int(int intno, int cpu) in get_desc_for_int() argument
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/ |
| D | power.c | 98 * proper cpu restore after PG.
231 uint32_t cpu = arch_proc_id(); in pm_state_set() local
234 core_desc[cpu].intenable = XTENSA_RSR("INTENABLE"); in pm_state_set()
238 core_desc[cpu].bctl = DSPCS.bootctl[cpu].bctl; in pm_state_set()
239 DSPCS.bootctl[cpu].bctl &= ~DSPBR_BCTL_WAITIPCG; in pm_state_set()
240 if (cpu == 0) { in pm_state_set()
241 soc_cpus_active[cpu] = false; in pm_state_set()
256 /* save CPU context here in pm_state_set()
259 * any changes to CPU context after _save_core_context in pm_state_set()
264 _save_core_context(cpu); in pm_state_set()
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| /Zephyr-Core-3.5.0/soc/posix/inf_clock/ |
| D | soc.c | 8 * For all purposes, Zephyr threads see a CPU running at an infinitely high
15 * The HW models raising an interrupt will "awake the cpu" by calling
44 * Helper function which changes the status of the CPU (halted or running)
50 * This is how the idle thread halts the CPU and gets halted until the HW models
51 * raise a new interrupt; and how the HW models awake the CPU, and wait for it
64 * HW models shall call this function to "awake the CPU"
69 /* We change the CPU to running state (we awake it), and block this in posix_interrupt_raised()
70 * thread until the CPU is halted again in posix_interrupt_raised()
78 * the idle loop will call this function to set the CPU to "sleep".
79 * Others may also call this function with care. The CPU will be set to sleep
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| /Zephyr-Core-3.5.0/dts/bindings/timer/ |
| D | nuclei,systimer.yaml | 24 clk-divider specifies the division ratio to the CPU frequency that
26 This property supports the case that the system timer and CPU use
30 For example, the CPU clock frequency is 108MHz, and the system timer
31 uses 27MHz, which is the CPU clock divided by 4.
32 In this case, the CPU clock frequency is defined in the CPU node
45 that CPU clock frequency divided by (2^2=)4, or 27MHz.
|
| /Zephyr-Core-3.5.0/samples/bluetooth/peripheral_hr/ |
| D | prj_minimal.conf | 62 # BT RX : STACK: unused 576 usage 448 / 1024 (43 %); CPU: 0 %
63 # BT RX pri : STACK: unused 260 usage 188 / 448 (41 %); CPU: 0 %
64 # BT ECC : STACK: unused 256 usage 888 / 1144 (77 %); CPU: 1 %
65 # BT TX : STACK: unused 296 usage 344 / 640 (53 %); CPU: 0 %
66 # thread_analyzer : STACK: unused 128 usage 384 / 512 (75 %); CPU: 1 %
67 # sysworkq : STACK: unused 856 usage 168 / 1024 (16 %); CPU: 0 %
68 # logging : STACK: unused 232 usage 536 / 768 (69 %); CPU: 0 %
69 # idle 00 : STACK: unused 208 usage 48 / 256 (18 %); CPU: 97 %
70 # main : STACK: unused 576 usage 448 / 1024 (43 %); CPU: 0 %
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| /Zephyr-Core-3.5.0/boards/arm64/khadas_edgev/ |
| D | khadas_edgev.dts | 22 /delete-node/ cpu@1;
23 /delete-node/ cpu@2;
24 /delete-node/ cpu@3;
25 /delete-node/ cpu@4;
26 /delete-node/ cpu@5;
|
| /Zephyr-Core-3.5.0/dts/arm64/nxp/ |
| D | nxp_ls1046a.dtsi | 18 cpu@0 {
19 device_type = "cpu";
23 cpu@1 {
24 device_type = "cpu";
28 cpu@2 {
29 device_type = "cpu";
33 cpu@3 {
34 device_type = "cpu";
|
| /Zephyr-Core-3.5.0/soc/arm/arm/musca_b1/ |
| D | soc.c | 21 * @brief Wake up CPU 1 from another CPU, this is platform specific.
26 /* Set the Initial Secure Reset Vector Register for CPU 1 */ in wakeup_cpu1()
32 /* Set the CPU Boot wait control after reset */ in wakeup_cpu1()
37 * @brief Get the current CPU ID, this is platform specific.
39 * @return Current CPU ID
|
| /Zephyr-Core-3.5.0/doc/kernel/services/smp/ |
| D | smp.rst | 8 "symmetric" in the sense that no specific CPU is treated specially by
25 purposes (e.g. for testing, or to reserve a physical CPU for running
40 does not: the fact that your CPU will not be interrupted while you are
41 in your critical section says nothing about whether a different CPU
52 needed to wait for the other CPU to exit the lock. The default Zephyr
71 recursive semantics above, spinlocks in single-CPU contexts produce
96 CPU Mask
106 By default, new threads can run on any CPU. Calling
107 :c:func:`k_thread_cpu_mask_disable` with a particular CPU ID will prevent
108 that thread from running on that CPU in the future. Likewise
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