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/Zephyr-latest/tests/drivers/spi/spi_controller_peripheral/
DKconfig9 0: CPOL 0 (Active high), CPHA 0 (leading)
10 1: CPOL 0 (Active high), CPHA 1 (trailing)
11 2: CPOL 1 (Active low), CPHA 0 (leading)
12 3: CPOL 1 (Active low), CPHA 1 (trailing)
DREADME.txt3 In each test, both instances get identical configuration (CPOL, CPHA, bitrate, etc.).
/Zephyr-latest/dts/bindings/wifi/
Dnordic,nrf70-qspi.yaml33 qspi-cpha:
36 Set to indicate phase starts with asserted half-phase (CPHA=1).
43 The driver using this property requires also use `cpha`.
/Zephyr-latest/boards/shields/x_nucleo_bnrg2a1/
Dx_nucleo_bnrg2a1.overlay21 spi-cpha; /* CPHA=1 */
/Zephyr-latest/boards/shields/x_nucleo_wb05kn1/
Dx_nucleo_wb05kn1_spi.overlay22 spi-cpha; /* CPHA=1 */
/Zephyr-latest/dts/bindings/mtd/
Dnordic,qspi-nor.yaml82 cpha:
85 Set to indicate phase starts with asserted half-phase (CPHA=1).
92 For this driver using this property requires also using cpha.
/Zephyr-latest/dts/bindings/mspi/
Dmspi-device.yaml71 MSPI_CPP_MODE_0: CPOL=0, CPHA=0
72 MSPI_CPP_MODE_1: CPOL=0, CPHA=1
73 MSPI_CPP_MODE_2: CPOL=1, CPHA=0
74 MSPI_CPP_MODE_3: CPOL=1, CPHA=1
/Zephyr-latest/dts/bindings/spi/
Dnxp,dspi.yaml54 This field is valid only when the CPHA bit in the CTAR register is 0.
60 supported for CPHA = 1.
Dnordic,nrf-spim.yaml37 of SCK (leading or trailing, depending on the CPHA setting used) until
Dspi-device.yaml48 spi-cpha:
/Zephyr-latest/samples/subsys/fs/fs_sample/boards/
Dnucleo_f429zi.overlay19 spi-clock-mode-cpha;
/Zephyr-latest/drivers/spi/
Dspi_sedi.c42 uint32_t word_size, cpol, cpha, loopback; in spi_sedi_configure() local
52 /* CPOL and CPHA */ in spi_sedi_configure()
54 cpha = SPI_MODE_GET(config->operation) & SPI_MODE_CPHA; in spi_sedi_configure()
56 if ((cpol == 0) && (cpha == 0)) { in spi_sedi_configure()
59 } else if ((cpol == 0) && (cpha == 1U)) { in spi_sedi_configure()
62 } else if ((cpol == 1) && (cpha == 0U)) { in spi_sedi_configure()
Dspi_bitbang.c125 int cpha = 0; in spi_bitbang_transceive() local
133 cpha = 1; in spi_bitbang_transceive()
185 if (!loop && do_read && !cpha) { in spi_bitbang_transceive()
194 if (!loop && do_read && cpha) { in spi_bitbang_transceive()
Dspi_numaker.c42 * CPOL/CPHA = 0/0 --> SPI_MODE_0
43 * CPOL/CPHA = 0/1 --> SPI_MODE_1
44 * CPOL/CPHA = 1/0 --> SPI_MODE_2
45 * CPOL/CPHA = 1/1 --> SPI_MODE_3
Dspi_rpi_pico_pio.c206 uint32_t cpha = 0; in spi_pico_pio_configure() local
263 cpha = 1; in spi_pico_pio_configure()
272 if ((cpol != 0) || (cpha != 0)) { in spi_pico_pio_configure()
358 if ((cpol == 0) && (cpha == 0)) { in spi_pico_pio_configure()
363 } else if ((cpol == 1) && (cpha == 1)) { in spi_pico_pio_configure()
369 LOG_ERR("Not supported: cpol=%d, cpha=%d\n", cpol, cpha); in spi_pico_pio_configure()
Dspi_xmc4xxx.c197 bool CPHA = SPI_MODE_GET(settings) & SPI_MODE_CPHA; in spi_xmc4xxx_configure() local
236 if (!CPOL && !CPHA) { in spi_xmc4xxx_configure()
238 } else if (!CPOL && CPHA) { in spi_xmc4xxx_configure()
240 } else if (CPOL && !CPHA) { in spi_xmc4xxx_configure()
242 } else if (CPOL && CPHA) { in spi_xmc4xxx_configure()
Dspi_xec_qmspi.c93 * SPI signalling mode: CPOL and CPHA
95 * CPHA = 0 Transmitter changes data on trailing of preceding clock cycle.
100 * Mode CPOL CPHA
105 * MEC1501 has three controls, CPOL, CPHA for output and CPHA for input.
/Zephyr-latest/samples/drivers/led/led_strip/boards/
Dmimxrt1050_evk_mimxrt1052_hyperflash.overlay19 spi-cpha;
Dmimxrt1050_evk_qspi.overlay19 spi-cpha;
Desp32c3_devkitm.overlay22 spi-cpha;
Desp32s2_saola.overlay22 spi-cpha;
Desp32s3_devkitm_procpu.overlay22 spi-cpha;
/Zephyr-latest/dts/bindings/sdhc/
Dzephyr,sdhc-spi-slot.yaml22 spi-clock-mode-cpha:
/Zephyr-latest/dts/bindings/mipi-dbi/
Dmipi-dbi-spi-device.yaml26 mipi-cpha:
/Zephyr-latest/boards/espressif/esp32c3_rust/
Desp32c3_rust.dts74 spi-cpha;

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