Searched full:cmr (Results 1 – 8 of 8) sorted by relevance
40 reg-cmr:43 Alternate value of the CMR (Channel Mode Register) register.56 is configured,see reg-cmr. It can be used as trigger for both input
53 uint32_t cmr; in sam_pwm_set_cycles() local68 cmr = PWM_CMR_CPRE_CLKA; in sam_pwm_set_cycles()71 cmr |= PWM_CMR_CPOL; in sam_pwm_set_cycles()75 if (pwm->PWM_CH_NUM[channel].PWM_CMR != cmr) { in sam_pwm_set_cycles()78 pwm->PWM_CH_NUM[channel].PWM_CMR = cmr; in sam_pwm_set_cycles()
70 LPTMR1->CMR = 0xFFFFFFFF; in cntr_start()116 * If the CMR is 0, the hardware trigger will remain asserted until in cntr_cmp_set()117 * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be in cntr_cmp_set()124 LPTMR1->CMR = value; in cntr_cmp_set()
10 CMr+0nRNEXhu5CeVOo5sO92sOsgQyIdJu94xccsKJ5XTORgBCVqvaZQJoDvAFC5j
384 uint8_t cmr; in can_sja1000_send() local422 cmr = CAN_SJA1000_CMR_SRR; in can_sja1000_send()424 cmr = CAN_SJA1000_CMR_TR; in can_sja1000_send()428 cmr |= CAN_SJA1000_CMR_AT; in can_sja1000_send()431 can_sja1000_write_reg(dev, CAN_SJA1000_CMR, cmr); in can_sja1000_send()
57 /* Command Register (CMR) bits */
138 SYSTEM_TIMER_INSTANCE->CMR = CYCLES_PER_TICK; in sys_clock_driver_init()
110 return (config->base->CMR & LPTMR_CMR_COMPARE_MASK) + 1U; in mcux_lptmr_get_top_value()
