| /Zephyr-Core-3.5.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/ |
| D | test_stm32_clock_configuration_i2c.c | 28 static void i2c_set_clock(const struct stm32_pclken *clk) in i2c_set_clock() argument
35 (clock_control_subsys_t) clk, in i2c_set_clock()
43 if (clk->bus == STM32_SRC_HSI) { in i2c_set_clock()
47 } else if (clk->bus == STM32_SRC_SYSCLK) { in i2c_set_clock()
52 zassert_true(0, "Unexpected domain clk (0x%x)", dev_actual_clk_src); in i2c_set_clock()
55 /* Test status of the used clk source */ in i2c_set_clock()
57 (clock_control_subsys_t)clk); in i2c_set_clock()
58 zassert_true((status == CLOCK_CONTROL_STATUS_ON), "I2C1 clk src must to be on"); in i2c_set_clock()
60 /* Test get_rate(srce clk) */ in i2c_set_clock()
62 (clock_control_subsys_t) clk, in i2c_set_clock()
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| D | test_stm32_clock_configuration_i2s.c | 52 zassert_true(0, "Unexpected domain clk (0x%x)", dev_actual_clk_src); in ZTEST()
55 /* Test get_rate(srce clk) */ in ZTEST()
59 zassert_true((r == 0), "Could not get I2S clk srce freq"); in ZTEST()
63 "Expected freq: %d Hz. Actual clk: %d Hz", in ZTEST()
68 /* Test clock_off(gating clk) */ in ZTEST()
71 zassert_true((r == 0), "Could not disable I2S gating clk"); in ZTEST()
73 zassert_true(!__HAL_RCC_SPI2_IS_CLK_ENABLED(), "I2S2 gating clk should be off"); in ZTEST()
74 TC_PRINT("I2S2 gating clk off\n"); in ZTEST()
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| D | test_stm32_clock_configuration_lptim.c | 60 zassert_true(0, "Unexpected domain clk (%d)", dev_actual_clk_src); in ZTEST()
63 /* Test get_rate(srce clk) */ in ZTEST()
67 zassert_true((r == 0), "Could not get LPTIM1 clk srce freq"); in ZTEST()
83 zassert_true((r == 0), "Could not get LPTIM1 clk freq"); in ZTEST()
96 zassert_true((r == 0), "Could not disable LPTIM1 gating clk"); in ZTEST()
98 zassert_true(!__HAL_RCC_LPTIM1_IS_CLK_ENABLED(), "LPTIM1 gating clk should be off"); in ZTEST()
99 TC_PRINT("LPTIM1 gating clk off\n"); in ZTEST()
101 /* Test clock_off(domain clk) */ in ZTEST()
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| D | test_stm32_clock_configuration_adc.c | 98 zassert_true(0, "Unexpected src clk (%d)", dev_actual_clk_src); in ZTEST()
101 /* Test status of the used clk source */ in ZTEST()
104 zassert_true((status == CLOCK_CONTROL_STATUS_ON), "ADC1 clk src must to be on"); in ZTEST()
106 /* Test get_rate(srce clk) */ in ZTEST()
110 zassert_true((r == 0), "Could not get ADC1 clk srce freq"); in ZTEST()
129 zassert_true((r == 0), "Could not disable ADC1 gating clk"); in ZTEST()
131 zassert_true(!ADC_IS_CLK_ENABLED(), "ADC1 gating clk should be off"); in ZTEST()
132 TC_PRINT("ADC1 gating clk off\n"); in ZTEST()
134 /* Test clock_off(domain clk) */ in ZTEST()
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| /Zephyr-Core-3.5.0/drivers/usb/device/ |
| D | usb_dc_dw_stm32.h | 22 static inline int clk_enable_st_stm32f4_fsotg(const struct usb_dw_stm32_clk *const clk) in clk_enable_st_stm32f4_fsotg() argument
26 if (!device_is_ready(clk->dev)) { in clk_enable_st_stm32f4_fsotg()
30 if (clk->pclken_len > 1) { in clk_enable_st_stm32f4_fsotg()
33 ret = clock_control_configure(clk->dev, in clk_enable_st_stm32f4_fsotg()
34 (void *)&clk->pclken[1], in clk_enable_st_stm32f4_fsotg()
40 ret = clock_control_get_rate(clk->dev, in clk_enable_st_stm32f4_fsotg()
41 (void *)&clk->pclken[1], in clk_enable_st_stm32f4_fsotg()
52 return clock_control_on(clk->dev, (void *)&clk->pclken[0]); in clk_enable_st_stm32f4_fsotg()
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| /Zephyr-Core-3.5.0/dts/bindings/i2c/ |
| D | atmel,sam-i2c-twim.yaml | 20 std-clk-slew-lim = <0>;
21 std-clk-strength-low = "0.5";
25 hs-clk-slew-lim = <0>;
26 hs-clk-strength-high = "0.5";
27 hs-clk-strength-low = "0.5";
54 std-clk-slew-lim:
59 std-clk-strength-low to fine tune the TWCK slope.
66 std-clk-strength-low:
114 hs-clk-slew-lim:
119 should be adjusted with both hs-clk-strength-high and
[all …]
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| /Zephyr-Core-3.5.0/tests/net/ptp/clock/src/ |
| D | main.c | 308 const struct device *clk; in iface_cb() local
315 clk = net_eth_get_ptp_clock(iface); in iface_cb()
316 if (!clk) { in iface_cb()
415 const struct device *clk; in test_ptp_clock_interfaces() local
419 clk = net_eth_get_ptp_clock(eth_interfaces[idx]); in test_ptp_clock_interfaces()
420 zassert_not_null(clk, "Clock not found for interface %p\n", in test_ptp_clock_interfaces()
424 clk = net_eth_get_ptp_clock(eth_interfaces[idx]); in test_ptp_clock_interfaces()
425 zassert_not_null(clk, "Clock not found for interface %p\n", in test_ptp_clock_interfaces()
428 clk = net_eth_get_ptp_clock(eth_interfaces[non_ptp_interface]); in test_ptp_clock_interfaces()
429 zassert_is_null(clk, "Clock found for interface %p\n", in test_ptp_clock_interfaces()
[all …]
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| /Zephyr-Core-3.5.0/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/ |
| D | test_stm32_clock_configuration.c | 57 zassert_true((r == 0), "Could not configure SPI domain clk"); in ZTEST()
58 TC_PRINT("SPI1 domain clk configured\n"); in ZTEST()
60 /* Test clk source */ in ZTEST()
72 zassert_true(1, "Unexpected clk src (0x%x)", spi1_actual_domain_clk); in ZTEST()
75 /* Test get_rate(source clk) */ in ZTEST()
79 zassert_true((r == 0), "Could not get SPI clk freq"); in ZTEST()
83 "Expected SPI clk: %d. Actual: %d", in ZTEST()
96 "Expected SPI clk freq: %d. Actual: %d", in ZTEST()
108 /* Test clock_off(domain clk) */ in ZTEST()
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| /Zephyr-Core-3.5.0/boards/arm/sam4l_ek/ |
| D | sam4l_ek.dts | 71 clk = <4>;
81 std-clk-slew-lim = <0>;
82 std-clk-strength-low = "0.5";
86 hs-clk-slew-lim = <0>;
87 hs-clk-strength-high = "0.5";
88 hs-clk-strength-low = "0.5";
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| /Zephyr-Core-3.5.0/drivers/clock_control/ |
| D | clock_control_smartbond.c | 116 enum smartbond_clock clk = (enum smartbond_clock)(sub_system); in smartbond_clock_control_on() local
120 switch (clk) { in smartbond_clock_control_on()
158 enum smartbond_clock clk = (enum smartbond_clock)(sub_system); in smartbond_clock_control_off() local
162 switch (clk) { in smartbond_clock_control_off()
207 static enum smartbond_clock smartbond_source_clock(enum smartbond_clock clk) in smartbond_source_clock() argument
222 if (clk == SMARTBOND_CLK_SYS_CLK) { in smartbond_source_clock()
223 clk = sys_clk_src[CRG_TOP->CLK_CTRL_REG & in smartbond_source_clock()
227 if (clk == SMARTBOND_CLK_LP_CLK) { in smartbond_source_clock()
228 clk = lp_clk_src[(CRG_TOP->CLK_CTRL_REG & in smartbond_source_clock()
232 return clk; in smartbond_source_clock()
[all …]
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| D | clock_control_r8a7795_cpg_mssr.c | 117 struct rcar_cpg_clk *clk, in r8a7795_cpg_core_clock_endisable() argument
125 clk_info = rcar_cpg_find_clk_info_by_module_id(dev, clk->domain, clk->module); in r8a7795_cpg_core_clock_endisable()
131 if (clk->rate > 0) { in r8a7795_cpg_core_clock_endisable()
132 uintptr_t rate = clk->rate; in r8a7795_cpg_core_clock_endisable()
134 ret = rcar_cpg_set_rate(dev, (clock_control_subsys_t)clk, in r8a7795_cpg_core_clock_endisable()
153 struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys; in r8a7795_cpg_mssr_start_stop() local
160 if (clk->domain == CPG_MOD) { in r8a7795_cpg_mssr_start_stop()
165 ret = rcar_cpg_mstp_clock_endisable(DEVICE_MMIO_GET(dev), clk->module, enable); in r8a7795_cpg_mssr_start_stop()
167 } else if (clk->domain == CPG_CORE) { in r8a7795_cpg_mssr_start_stop()
168 ret = r8a7795_cpg_core_clock_endisable(dev, clk, enable); in r8a7795_cpg_mssr_start_stop()
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| D | clock_control_renesas_cpg_mssr.c | 84 LOG_ERR("%s: can't find clk info (domain %u module %u)", dev->name, domain, id); in rcar_cpg_find_clk_info_by_module_id()
222 struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys; in rcar_cpg_get_rate() local
233 clk_info = rcar_cpg_find_clk_info_by_module_id(dev, clk->domain, clk->module); in rcar_cpg_get_rate()
245 LOG_ERR("%s: clk (domain %u module %u) error (%lld) during getting out frequency", in rcar_cpg_get_rate()
246 dev->name, clk->domain, clk->module, ret); in rcar_cpg_get_rate()
249 LOG_ERR("%s: clk (domain %u module %u) frequency bigger then max uint value", in rcar_cpg_get_rate()
250 dev->name, clk->domain, clk->module); in rcar_cpg_get_rate()
264 struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys; in rcar_cpg_set_rate() local
278 clk_info = rcar_cpg_find_clk_info_by_module_id(dev, clk->domain, clk->module); in rcar_cpg_set_rate()
328 dev->name, clk->domain, clk->module, out_rate, u_rate); in rcar_cpg_set_rate()
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| /Zephyr-Core-3.5.0/dts/bindings/clock/ |
| D | intel,adsp-shim-clkctl.yaml | 9 adsp-clkctl-clk-wovcro:
14 adsp-clkctl-clk-lpro:
18 adsp-clkctl-clk-hpro:
22 adsp-clkctl-clk-ipll:
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| D | nuvoton,numaker-pcc.yaml | 15 - clock-module-index # Same as u32ModuleIdx on invoking BSP CLK driver CLK_SetModuleClock()
16 - clock-source # Same as u32ClkSrc on invoking BSP CLK driver CLK_SetModuleClock()
17 - clock-divider # Same as u32ClkDiv on invoking BSP CLK driver CLK_SetModuleClock()
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| D | st,stm32g0-hsi-clock.yaml | 8 It also produces a HSISYS secondary clk which can be used as system clock
31 It does not apply to HSI clk selected as peripheral source clock
32 (eg: RNG clk driven by HSI)
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| /Zephyr-Core-3.5.0/samples/sensor/lps22hh_i3c/boards/ |
| D | mimxrt685_evk_cm33.overlay | 14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
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| /Zephyr-Core-3.5.0/samples/sensor/lsm6dso_i2c_on_i3c/boards/ |
| D | mimxrt685_evk_cm33.overlay | 14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
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| /Zephyr-Core-3.5.0/dts/arm/st/f2/ |
| D | stm32f207.dtsi | 17 clock-names = "stmmaceth", "mac-clk-tx",
18 "mac-clk-rx", "mac-clk-ptp";
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| /Zephyr-Core-3.5.0/dts/arm/st/f4/ |
| D | stm32f407.dtsi | 17 clock-names = "stmmaceth", "mac-clk-tx",
18 "mac-clk-rx", "mac-clk-ptp";
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| /Zephyr-Core-3.5.0/dts/bindings/i3c/ |
| D | nxp,mcux-i3c.yaml | 25 clk-divider:
30 clk-divider-tc:
35 clk-divider-slow:
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| /Zephyr-Core-3.5.0/drivers/serial/ |
| D | uart_pl011_ambiq.h | 22 static inline int pl011_ambiq_clk_set(const struct device *dev, uint32_t clk) in pl011_ambiq_clk_set() argument
26 switch (clk) { in pl011_ambiq_clk_set()
47 static inline int clk_enable_ambiq_uart(const struct device *dev, uint32_t clk) in clk_enable_ambiq_uart() argument
50 return pl011_ambiq_clk_set(dev, clk); in clk_enable_ambiq_uart()
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| /Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/kwx/ |
| D | soc_kw4xz.c | 18 #define CLOCK_NODEID(clk) \ argument
19 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
21 #define CLOCK_DIVIDER(clk) \ argument
22 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
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| /Zephyr-Core-3.5.0/subsys/net/l2/ethernet/gptp/ |
| D | gptp_user_api.c | 57 const struct device *clk; in gptp_event_capture() local
66 clk = net_eth_get_ptp_clock(GPTP_PORT_IFACE(port)); in gptp_event_capture()
67 if (clk) { in gptp_event_capture()
68 ptp_clock_get(clk, slave_time); in gptp_event_capture()
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| /Zephyr-Core-3.5.0/drivers/memc/ |
| D | memc_stm32.c | 35 const struct device *clk; in memc_stm32_init() local
45 clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in memc_stm32_init()
47 if (!device_is_ready(clk)) { in memc_stm32_init()
52 r = clock_control_on(clk, (clock_control_subsys_t)&config->pclken); in memc_stm32_init()
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| /Zephyr-Core-3.5.0/dts/bindings/timer/ |
| D | nuclei,systimer.yaml | 21 clk-divider:
24 clk-divider specifies the division ratio to the CPU frequency that
44 Setting clk-divider to 2 specifies the system timer uses the clock
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