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41 (FDCAN_CCU->CCFG CDIV register bits). Note that the divisor is common to all
88 uint32_t cdiv; in can_stm32h7_get_core_clock() local97 cdiv = FIELD_GET(FDCANCCU_CCFG_CDIV, FDCAN_CCU->CCFG); in can_stm32h7_get_core_clock()98 if (cdiv == 0U) { in can_stm32h7_get_core_clock()101 *rate = rate_tmp / (cdiv << 1U); in can_stm32h7_get_core_clock()
