| /Zephyr-Core-3.7.0/modules/tflite-micro/ |
| D | CMakeLists.txt | 32 ${TENSORFLOW_LITE_MICRO_DIR}/python/tflite_micro/python_ops_resolver.cc
33 ${TENSORFLOW_LITE_MICRO_DIR}/signal/micro/kernels/fft_flexbuffers_generated_data.cc
34 ${TENSORFLOW_LITE_MICRO_DIR}/signal/micro/kernels/rfft.cc
35 ${TENSORFLOW_LITE_MICRO_DIR}/signal/micro/kernels/window.cc
36 ${TENSORFLOW_LITE_MICRO_DIR}/signal/micro/kernels/window_flexbuffers_generated_data.cc
37 ${TENSORFLOW_LITE_MICRO_DIR}/signal/src/rfft_float.cc
38 ${TENSORFLOW_LITE_MICRO_DIR}/signal/src/rfft_int16.cc
39 ${TENSORFLOW_LITE_MICRO_DIR}/signal/src/rfft_int32.cc
40 ${TENSORFLOW_LITE_MICRO_DIR}/signal/src/window.cc
41 ${TENSORFLOW_LITE_MICRO_DIR}/signal/src/kiss_fft_wrappers/kiss_fft_float.cc
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| /Zephyr-Core-3.7.0/include/zephyr/arch/arc/asm-compat/ |
| D | asm-macro-32-bit-gnu.h | 10 .irp cc,,.hi,.nz
11 .macro MOVR\cc d, s
12 mov\cc \d, \s
49 .irp cc,,.nz
50 .macro ADDR\cc d, s, v
51 add\cc \d, \s, \v
55 .irp cc,,.nz
56 .macro ADD2R\cc d, s, v
57 add2\cc \d, \s, \v
89 .irp cc,ne,eq
[all …]
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| D | asm-macro-64-bit-gnu.h | 10 .irp cc,,.hi,.nz
11 .macro MOVR\cc d, s
12 movl\cc \d, \s
61 .irp cc,,.nz
62 .macro ADDR\cc d, s, v
63 addl\cc \d, \s, \v
67 .irp cc,,.nz
68 .macro ADD2R\cc d, s, v
69 add2l\cc \d, \s, \v
101 .irp cc,ne,eq
[all …]
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| /Zephyr-Core-3.7.0/scripts/west_commands/zspdx/ |
| D | licenses.py | 85 "CC-BY-1.0",
86 "CC-BY-2.0",
87 "CC-BY-2.5",
88 "CC-BY-3.0",
89 "CC-BY-3.0-AT",
90 "CC-BY-3.0-US",
91 "CC-BY-4.0",
92 "CC-BY-NC-1.0",
93 "CC-BY-NC-2.0",
94 "CC-BY-NC-2.5",
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| /Zephyr-Core-3.7.0/include/zephyr/drivers/usb_c/ |
| D | usbc_tc.h | 161 * See Table 4-31 CC Timing
167 * See Table 4-31 CC Timing
173 * the potential for USB PD signaling on CC as described in the state definitions.
174 * See Table 4-31 CC Timing
180 * the potential for USB PD signaling on CC as described in the state definitions.
181 * See Table 4-31 CC Timing
188 * See Table 4-31 CC Timing
195 * See Table 4-31 CC Timing
201 * See Table 4-31 CC Timing
208 * See Table 4-31 CC Timing
[all …]
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| /Zephyr-Core-3.7.0/subsys/bluetooth/host/ |
| D | hci_common.c | 28 struct bt_hci_evt_cmd_complete *cc; in bt_hci_cmd_complete_create() local
30 buf = bt_hci_evt_create(BT_HCI_EVT_CMD_COMPLETE, sizeof(*cc) + plen); in bt_hci_cmd_complete_create()
32 cc = net_buf_add(buf, sizeof(*cc)); in bt_hci_cmd_complete_create()
33 cc->ncmd = 1U; in bt_hci_cmd_complete_create()
34 cc->opcode = sys_cpu_to_le16(op); in bt_hci_cmd_complete_create()
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| /Zephyr-Core-3.7.0/subsys/usb/usb_c/ |
| D | usbc_tc_snk_states.c | 21 enum tc_cc_voltage_state cc; in sink_power_sub_states() local
26 /* Get the active CC line */ in sink_power_sub_states()
27 cc = tc->cc_polarity ? tc->cc2 : tc->cc1; in sink_power_sub_states()
29 if (cc == TC_CC_VOLT_RP_DEF) { in sink_power_sub_states()
36 } else if (cc == TC_CC_VOLT_RP_1A5) { in sink_power_sub_states()
44 } else if (cc == TC_CC_VOLT_RP_3A0) { in sink_power_sub_states()
88 * Allow the state machine to immediately check the state of CC lines and go into in tc_unattached_snk_entry()
89 * Attach.Wait state in case the Rp value is detected on the CC lines in tc_unattached_snk_entry()
104 * on at least one of its CC pins. in tc_unattached_snk_run()
147 /* Debounce the cc state */ in tc_attach_wait_snk_run()
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| D | usbc_tc_src_states.c | 55 * When in the UnattachedWait.SRC state, the port is discharging the CC pin
62 * 2: The port shall continue to provide an Rp termination on the CC pin not
66 * 3: The port shall provide an Rdch termination on the CC pin being
92 /* CC Debounce time should be enough time for VCONN to discharge */ in tc_unattached_wait_src_run()
128 /* Initialize the cc state to open */ in tc_attach_wait_src_entry()
150 /* Debounce the cc state */ in tc_attach_wait_src_run()
157 /* Wait for CC debounce */ in tc_attach_wait_src_run()
195 * cable, i.e., which CC pin is in the SRC.Rd state.
200 * port shall source current on this CC pin and monitor its state.
233 /* Set cc polarity */ in tc_attached_src_entry()
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| D | usbc_tc_common_internal.h | 31 /** Super state that opens the CC lines */
34 /** Super state that applies Rd to the CC lines */
43 /** Super state that applies Rp to the CC lines */
77 /** The cc state */
79 /** Voltage on CC pin */
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| /Zephyr-Core-3.7.0/drivers/disk/nvme/ |
| D | nvme_controller.c | 62 uint32_t cc, csts; in nvme_controller_disable() local
66 cc = nvme_mmio_read_4(regs, cc); in nvme_controller_disable()
71 enabled = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK; in nvme_controller_disable()
89 cc &= ~NVME_CC_REG_EN_MASK; in nvme_controller_disable()
90 nvme_mmio_write_4(regs, cc, cc); in nvme_controller_disable()
100 uint32_t cc, csts; in nvme_controller_enable() local
103 cc = nvme_mmio_read_4(regs, cc); in nvme_controller_enable()
108 enabled = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK; in nvme_controller_enable()
124 /* Initialization values for CC */ in nvme_controller_enable()
125 cc = 0; in nvme_controller_enable()
[all …]
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| /Zephyr-Core-3.7.0/cmake/compiler/xcc/ |
| D | generic.cmake | 3 set_ifndef(CC gcc)
5 find_program(CMAKE_C_COMPILER ${CROSS_COMPILE}${CC} PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH)
9 …message(FATAL_ERROR "Zephyr was unable to find ${CROSS_COMPILE}${CC}. Is the environment misconfig…
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| /Zephyr-Core-3.7.0/scripts/west_commands/tests/ |
| D | test_bossac.py | 161 def test_bossac_init(cc, req, get_cod_par, sup, runner_config, tmpdir): argument
183 assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS]
193 def test_bossac_create(cc, req, get_cod_par, sup, runner_config, tmpdir): argument
219 assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS]
229 def test_bossac_create_with_speed(cc, req, get_cod_par, sup, runner_config, tmpdir): argument
257 assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS_WITH_SPEED]
267 def test_bossac_create_with_flash_address(cc, req, get_cod_par, sup, argument
298 assert cc.call_args_list == [
310 def test_bossac_create_with_omit_address(cc, req, bcfg_ini, sup, argument
336 assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS]
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| D | test_mdb.py | 203 def test_flash_nsim(require, cc, test_case, mdb_nsim): argument
206 cc.assert_called_once_with(test_case['o'], cwd=RC_BUILD_DIR)
220 def test_multicores_nsim(require, pii, cc, test_case, mdb_nsim): argument
224 cc.assert_has_calls(cc_calls)
232 def test_flash_hw_no_hl(require, cc, test_case, mdb_hw_no_hl, tmpdir): argument
235 cc.assert_called_once_with(test_case['o'], cwd=tmpdir)
240 def test_flash_hw_hl(require, cc, test_case, mdb_hw_hl, tmpdir): argument
243 cc.assert_called_once_with(test_case['o'], cwd=tmpdir)
248 def test_flash_hw_err(require, cc, test_case, mdb_hw_no_hl): argument
283 def test_multicores_hw_no_hl(require, pii, cc, test_case, mdb_hw_no_hl, tmpdir): argument
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| D | test_gd32isp.py | 50 def test_gd32isp_init(cc, req, runner_config): argument
54 assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS_DEFAULT]
59 def test_gd32isp_create(cc, req, runner_config): argument
71 assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS]
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| D | test_dediprog.py | 51 def test_dediprog_init(cc, req, tc, runner_config): argument
57 assert cc.call_args_list == [call(EXPECTED_COMMAND[tc])]
66 def test_dediprog_create(cc, req, tc, runner_config): argument
77 assert cc.call_args_list == [call(EXPECTED_COMMAND[tc])]
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| D | test_pyocd.py | 169 def test_flash(require, cc, pyocd_args, expected, pyocd): argument
172 cc.assert_called_once_with(expected)
193 def test_debugserver(require, cc, pyocd_args, expected, pyocd): argument
196 cc.assert_called_once_with(expected)
213 def test_flash_args(require, cc, bc, pyocd_args, flash_addr, expected, pyocd): argument
219 cc.assert_called_once_with(expected)
243 def test_debugserver_args(require, cc, bc, pyocd_args, expected, pyocd): argument
247 cc.assert_called_once_with(expected)
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| D | test_stm32flash.py | 78 def test_stm32flash_init(cc, req, action, runner_config): argument
92 assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS[action]]
97 def test_stm32flash_create(cc, req, action, runner_config): argument
112 assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS[action]]
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| /Zephyr-Core-3.7.0/doc/hardware/peripherals/ |
| D | tcpc.rst | 18 * CC control and sensing:
19 The TCPC implements logic for controlling the CC pin pull-up and pull-down
21 present on the CC pin.
25 on the CC lines.
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| /Zephyr-Core-3.7.0/drivers/counter/ |
| D | counter_nrfx_rtc.c | 58 /* Store channel interrupt pending and CC adjusted flags. */
133 /* From Product Specification: If a CC register value is 0 when in skip_zero_on_custom_top()
170 /** @brief Handle case when CC value equals COUNTER+1.
172 * RTC will not generate event if CC value equals COUNTER+1. If such CC is
174 * expire before expected value, CC is set to COUNTER+2. If COUNTER progressed
177 * that CC value will generate event.
179 * Additionally, an information about CC adjustment is stored. This information
180 * is used in the callback to return original CC value which was requested by
202 * Setting CC algorithm takes into account:
247 "Expected that CC interrupt is disabled."); in set_cc()
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| /Zephyr-Core-3.7.0/drivers/timer/ |
| D | nrf_rtc_timer.c | 105 /* 24 least significant bits represent target CC value */ in absolute_time_to_cc()
231 * and properly adjusts CC values that are too near in the future to guarantee
235 * @param[in] chan A channel for which a new CC value is to be set.
237 * @param[in] req_cc Requested CC register value to be set.
239 * @param[in] exact Use @c false to allow CC adjustment if @c req_cc value is
241 * Use @c true to disallow CC adjustment. The function can
245 * @retval 0 The requested CC has been set successfully.
246 * @retval -EINVAL The requested CC value could not be reliably set.
258 * is N, a value of N+2 written to the CC register is guaranteed to in set_alarm()
260 * value can be missed when the previous CC value is N+1 and the write in set_alarm()
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| /Zephyr-Core-3.7.0/soc/nordic/nrf53/ |
| D | sync_rtc.c | 49 * NET: setup RTC CC for arbitrary offset from now, setup PPI from RTC_COMPARE to IPC_SEND
50 * Record value set to CC.
60 * When NET RTC captures IPC event it takes CC value and knowing CC value previously
159 uint32_t cc; in remote_callback() local
163 cc = z_nrf_rtc_timer_compare_read(channels.ch.rtc); in remote_callback()
174 z_nrf_rtc_timer_set(channels.ch.rtc, cc + cc + RTC_SYNC_ARBITRARY_DELAY, in remote_callback()
179 nrf53_sync_offset = cc - RTC_SYNC_ARBITRARY_DELAY - 2 * sync_cc; in remote_callback()
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| D | soc.c | 45 /* Mask of CC channels capable of generating interrupts, see nrf_rtc_timer.c */
136 /* The CC is in selected mask and is can generate an interrupt. */ in rtc_ticks_to_next_event_get()
137 uint32_t cc = nrf_rtc_cc_get(rtc, chan); in rtc_ticks_to_next_event_get() local
138 uint32_t ticks_to_fire = rtc_counter_sub(cc, cntr); in rtc_ticks_to_next_event_get()
155 /* CC that fires no earlier than already found. */ in rtc_ticks_to_next_event_get()
244 /* The CC for pretick needs to be updated. */ in z_arm_on_enter_cpu_idle_prepare()
252 /* Let's check if we updated CC on time, so that the CC can in z_arm_on_enter_cpu_idle_prepare()
263 * pretick CC or has just expired, so the pretick event in z_arm_on_enter_cpu_idle_prepare()
275 /* The CC for pretick doesn't need to be updated, however in z_arm_on_enter_cpu_idle_prepare()
280 /* If the CC for pretick is set on time, so the pretick CC event can be reliably in z_arm_on_enter_cpu_idle_prepare()
[all …]
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| /Zephyr-Core-3.7.0/cmake/compiler/gcc/ |
| D | generic.cmake | 3 set_ifndef(CC gcc)
5 find_program(CMAKE_C_COMPILER ${CROSS_COMPILE}${CC} PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH)
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| /Zephyr-Core-3.7.0/dts/bindings/timer/ |
| D | nordic,nrf-timer.yaml | 14 cc-num:
17 description: Number of capture/compare (CC) registers available
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| /Zephyr-Core-3.7.0/dts/bindings/rtc/ |
| D | nordic,nrf-rtc.yaml | 14 cc-num:
18 Number of compare (CC) registers available.
|
