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/Zephyr-Core-3.4.0/arch/
DKconfig1 # General architecture configuration options
14 # Architecture symbols
26 ARC architecture
39 ARM architecture
53 ARM64 (AArch64) architecture
61 MIPS architecture
75 SPARC architecture
95 x86 architecture
105 Nios II Gen 2 architecture
121 RISCV architecture
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/Zephyr-Core-3.4.0/arch/arm/core/aarch32/cortex_a_r/
DKconfig116 From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
117 The Armv7-R architecture implements a traditional Arm architecture with
118 multiple modes and supports a Protected Memory System Architecture
136 From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
137 The Armv8-R architecture targets at the Real-time profile. It introduces
139 Protected Memory System Architecture (PMSA) based on a Memory Protection
/Zephyr-Core-3.4.0/doc/hardware/porting/
Darch.rst3 Architecture Porting Guide
6 An architecture port is needed to enable Zephyr to run on an :abbr:`ISA
7 (instruction set architecture)` or an :abbr:`ABI (Application Binary
20 An architecture port can be divided in several parts; most are required and
23 * **The early boot sequence**: each architecture has different steps it must
26 * **Interrupt and exception handling**: each architecture handles asynchronous
33 and architecture-dependent, and thread abortion possibly as well (required).
36 controller are tied to the architecture (some required, some optional).
39 architecture-specific implementation for performance reasons (required).
44 * **Fault management**: for implementing architecture-specific debug help and
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/Zephyr-Core-3.4.0/doc/services/dsp/
Dindex.rst10 The DSP API provides an architecture agnostic way for signal processing.
11 Currently, the API will work on any architecture but will likely not be
15 Architecture Status
44 Optimizing for your architecture
47 If your architecture is showing as ``Unoptimized``, it's possible to add a new
53 linked in at :file:`subsys/dsp/CMakeLists.txt`. To add architecture-specific attributes,
/Zephyr-Core-3.4.0/kernel/include/
Dkernel_arch_interface.h9 * @brief Internal kernel APIs implemented at the architecture layer.
11 * Not all architecture-specific defines are here, APIs that are used
30 * @defgroup arch-timing Architecture timing APIs
35 * Architecture-specific implementation of busy-waiting
45 * @defgroup arch-threads Architecture thread APIs
88 * by the architecture. It is the same data structure stored in the
123 * architecture code to assume that it has any particular value at any
181 * @note For ARM architecture, disabling floating point preservation may only
195 * This API depends on each architecture implimentation. If the architecture
202 * @param options architecture dependent options
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/Zephyr-Core-3.4.0/arch/arm64/core/
DKconfig150 From https://developer.arm.com/products/architecture/cpu-architecture/a-profile:
151 The Armv8-A architecture introduces the ability to use 64-bit and
157 compatibility with the Armv7-A architecture and enhances that profile
174 From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
175 The Armv8-R architecture targets at the Real-time profile. It introduces
177 Protected Memory System Architecture (PMSA) based on a Memory Protection
/Zephyr-Core-3.4.0/drivers/ethernet/
DKconfig.dsa1 # Distributed Switch Architecture [DSA] configuration options
8 bool "Distributed Switch Architecture support"
11 Enable Distributed Switch Architecture support. For now it
/Zephyr-Core-3.4.0/boards/posix/doc/
Dbsim_boards_design.rst6 This page covers the design, architecture and rationale, of the
50 With the POSIX architecture we provided an overall
90 The native_posix board shares the :ref:`POSIX architecture<Posix arch>`
108 The basic architecture layering of these boards is as follows:
110 - The architecture, SOC and board components of Zephyr are replaced with
112 - The architecture (arch) is the Zephyr :ref:`POSIX architecture<Posix arch>`
116 - The POSIX architecture provides an adaptation from the Zephyr arch API
118 See :ref:`POSIX arch architecture<posix_arch_architecture>`
142 Overall architecture in a Zephyr application in an embedded target vs a bsim
157 The threading description, as well as the general SOC and board architecture
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Darch_soc.rst3 The POSIX architecture
14 The POSIX architecture, in combination with the inf_clock SOC layer,
15 provides the foundation, architecture and SOC layers for a set of virtual test
22 Zephyr application, eliminating the need for architecture-specific
27 The POSIX architecture is not related and should not be confused with the
61 The POSIX architecture is known to **not** work on macOS due to
97 `Rationale for this port`_ and :ref:`Architecture<posix_arch_architecture>`
233 The drivers and HW models for this architecture will hide this from the
258 As instructions are translated to the host architecture, and the target CPU and
286 Architecture and design
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/Zephyr-Core-3.4.0/soc/riscv/riscv-privileged/telink_b91/
DKconfig.soc5 prompt "CPU Architecture of SoC"
9 bool "RISCV32 CPU Architecture"
/Zephyr-Core-3.4.0/subsys/testsuite/arch/unit_testing/
DKconfig11 The unit_testing architecture identifies itself as X86 for basic
21 The unit testing architecture is expected to always have access to a
/Zephyr-Core-3.4.0/doc/services/pm/
Doverview.rst5 are designed to be architecture and SOC independent. This enables power
9 The architecture and SOC independence is achieved by separating the core
/Zephyr-Core-3.4.0/doc/services/debugging/
Dcoredump.rst58 4. Start the debugger corresponding to the target architecture.
211 architecture-specific block, and multiple memory blocks. All numbers in
237 - Indicate which target (e.g. architecture or SoC) so the parser
253 Architecture-specific Block
256 The architecture-specific block contains the byte stream of data specific
257 to the target architecture (e.g. CPU registers)
259 .. list-table:: Architecture-specific Block
268 - ``A`` to indicate this is a architecture-specific block.
272 architecture specific block parser.
280 - Contains target architecture specific data.
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/Zephyr-Core-3.4.0/include/zephyr/arch/
Dstructs.h8 * The purpose of this file is to provide essential/minimal architecture-
32 /* Default definitions when no architecture specific definitions exist. */
34 /* Per CPU architecture specifics (empty) */
Darch_inlines.h3 * include based on the selected architecture.
36 #error "Unknown Architecture"
/Zephyr-Core-3.4.0/include/zephyr/
Dfatal.h31 * Invokes architecture-specific code to power off or halt the system in
45 * unconditionally. Depending on architecture support, this may be
70 * Called by architecture code upon a fatal error.
72 * This function dumps out architecture-agnostic information about the error
/Zephyr-Core-3.4.0/doc/kernel/services/other/
Dfloat.rst12 the Intel x86 architecture, the SPARC architecture and ARCv2 SoCs
14 are architecture specific.
59 floating point registers. Depending upon the underlying CPU architecture,
75 ARM Cortex-M architecture (with the Floating Point Extension)
82 On the ARM Cortex-M architecture with the Floating Point Extension, the kernel
118 architecture, minimizing interrupt latency, when the floating
136 ARM64 architecture
145 On the ARM64 (Aarch64) architecture the kernel treats each thread as a FPU
162 ARCv2 architecture
165 On the ARCv2 architecture, the kernel treats each thread as a non-user
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/Zephyr-Core-3.4.0/boards/posix/nrf52_bsim/
DKconfig5 # The following file is normally parsed only for the ARM architecture, which is
7 # the simulated nrf52_bsim board, which uses the POSIX architecture, the file
/Zephyr-Core-3.4.0/doc/security/
Dsecurity-overview.rst26 1. **Secure Development:** Defines the system architecture and
31 to enforce them. A security architecture of the system and
100 scoped for future releases. The Zephyr runtime architecture is a
139 The security architecture is based on a monolithic design where the
248 software security. Furthermore, a system architecture document shall be
251 System Architecture
254 .. figure:: media/security-zephyr-system-architecture.png
256 Figure 2: Zephyr System Architecture
258 A high-level schematic of the Zephyr system architecture is given in
259 Figure 2. It separates the architecture into an OS part (*kernel + OS
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/Zephyr-Core-3.4.0/arch/arm64/
DKconfig1 # ARM64 architecture configuration options
28 When this option is selected, the architecture interrupt control
/Zephyr-Core-3.4.0/subsys/bluetooth/controller/ll_sw/openisa/hal/RV32M1/
Dswi.h18 /* Split architecture uses max. two SWI */
35 #error "CTRL architecture not defined"
/Zephyr-Core-3.4.0/scripts/pylib/twister/twisterlib/
Dquarantine.py29 def get_matched_quarantine(self, testname, platform, architecture, simulation): argument
30 qelem = self.quarantine.get_matched_quarantine(testname, platform, architecture, simulation)
98 architecture: str,
110 … and (matched := _is_element_matched(architecture, qelem.architectures)) is False):
/Zephyr-Core-3.4.0/subsys/testsuite/ztest/include/zephyr/arch/
Dcpu.h15 /* Architecture thread structure */
34 /* Architecture functions */
/Zephyr-Core-3.4.0/tests/kernel/fpu_sharing/generic/src/
Dfloat_context.h16 * Each architecture must define the following structures (which may be empty):
20 * Each architecture must also define the following macros:
26 * Each architecture shall also have custom implementations of:
168 #error "Architecture must provide the following definitions:\n"
/Zephyr-Core-3.4.0/arch/posix/
DKconfig20 architecture.
21 (In this architecture only part of the thread status is kept in the Zephyr

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