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/Zephyr-Core-3.6.0/boards/arm/ast1030_evb/
Dast1030_evb.dts2 * Copyright (c) 2021 Aspeed Technology Inc.
8 #include <aspeed/ast10x0.dtsi>
11 model = "Aspeed AST1030 Evaluation board";
12 compatible = "aspeed,ast1030-evb";
DKconfig.board3 # Aspeed AST1030 evaluation board configuration
5 # Copyright (c) 2021 Aspeed Technology Inc.
8 bool "ASPEED AST1030 Evaluation Board"
Dast1030_evb.yaml1 # Copyright (c) 2021 Aspeed Technology Inc.
4 name: Aspeed AST1030-EVB
13 vendor: aspeed
DKconfig.defconfig3 # Aspeed AST1030 evaluation board configuration
5 # Copyright (c) 2021 Aspeed Technology Inc.
Dast1030_evb_defconfig3 # Copyright (c) 2021 Aspeed Technology Inc.
/Zephyr-Core-3.6.0/drivers/clock_control/
DKconfig.aspeed1 # Copyright (c) 2022 ASPEED Technology Inc.
5 bool "ASPEED clock control driver"
9 This option enables the clock driver for ASPEED AST10X0 series SOC.
/Zephyr-Core-3.6.0/drivers/reset/
DKconfig.aspeed1 # Copyright (c) 2022 ASPEED Technology Inc.
5 bool "ASPEED reset driver"
9 This option enables the reset driver for ASPEED AST10X0 series SOC.
/Zephyr-Core-3.6.0/soc/arm/aspeed/
DKconfig3 # Copyright (c) 2021 ASPEED Technology Inc.
13 default "aspeed"
15 source "soc/arm/aspeed/*/Kconfig.soc"
DKconfig.soc3 # Copyright (c) 2021 ASPEED Technology Inc.
5 source "soc/arm/aspeed/*/Kconfig.series"
DKconfig.defconfig3 # Copyright (c) 2021 ASPEED Technology Inc.
5 source "soc/arm/aspeed/*/Kconfig.defconfig.series"
Daspeed_util.h4 * Copyright (c) 2021 ASPEED Technology Inc.
53 /* Common reset control device name for all ASPEED SOC family */
DCMakeLists.txt3 # Copyright (c) 2021 ASPEED Technology Inc.
/Zephyr-Core-3.6.0/drivers/cache/
DKconfig.aspeed3 # Copyright (c) 2022 ASPEED Technology Inc.
6 bool "ASPEED external cache driver"
11 This option enables the CACHE driver for ASPEED AST10X0 series SOC.
DKconfig21 source "drivers/cache/Kconfig.aspeed"
/Zephyr-Core-3.6.0/soc/arm/aspeed/ast10x0/
DKconfig.series3 # Copyright (c) 2021 ASPEED Technology Inc.
6 bool "Aspeed AST10X0 Series"
19 Enable support for ASPEED AST10X0 series
DKconfig.defconfig.series3 # Copyright (c) 2021 ASPEED Technology Inc.
7 source "soc/arm/aspeed/ast10x0/Kconfig.defconfig.ast10*0"
DKconfig.soc3 # Copyright (c) 2021 ASPEED Technology Inc.
6 prompt "ASPEED AST10X0 Selection"
Dsboot.ld2 * Copyright (c) ASPEED Technology Inc.
Dnocache.ld2 * Copyright (c) ASPEED Technology Inc.
DKconfig.defconfig.ast10303 # Copyright (c) 2021 ASPEED Technology Inc.
DCMakeLists.txt1 # Copyright (c) 2021 ASPEED Technology Inc.
/Zephyr-Core-3.6.0/dts/bindings/reset/
Daspeed,ast10x0-reset.yaml1 # Copyright (c) 2022 Aspeed Technology Inc.
4 description: Aspeed AST10X0 Reset Controller
6 compatible: "aspeed,ast10x0-reset"
/Zephyr-Core-3.6.0/dts/bindings/clock/
Daspeed,ast10x0-clock.yaml1 # Copyright (c) 2022 Aspeed Technology Inc.
4 description: Aspeed AST10X0 Clock Controller
6 compatible: "aspeed,ast10x0-clock"
/Zephyr-Core-3.6.0/dts/arm/aspeed/
Dast10x0.dtsi4 * Copyright (c) 2021 ASPEED Technology Inc.
32 compatible = "aspeed,ast10x0-clock";
37 compatible = "aspeed,ast10x0-reset";
/Zephyr-Core-3.6.0/boards/arm/ast1030_evb/doc/
Dindex.rst10 Aspeed AST10x0 series SOCs. This board needs to be mated with
56 Aspeed to provide the schematic for this board.
80 `Aspeed Zephyr SDK User Guide`_ for more information.

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