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/Zephyr-latest/arch/arc/
DKconfig1 # ARC options
6 menu "ARC Options"
7 depends on ARC
10 default "arc"
16 This option signifies the use of an ARC EM CPU
23 This option signifies the use of an ARC HS CPU
27 prompt "ARC Instruction Set"
31 bool "ARC ISA v2"
38 v2 ISA for the ARC-HS & ARC-EM cores
41 bool "ARC ISA v3"
[all …]
/Zephyr-latest/boards/snps/emsdp/
DKconfig.emsdp1 # DesignWare ARC EM Software Development Platform board configuration
16 The ARC EM Software Development Platform (emsdp) is an FPGA based
17 development platform intended to support ARC licenses in developing
18 their software for the ARC EM processor family and ARC EM Subsystems.
19 It has the support for ARC EM4, EM5D, EM6, EM7D, EM9D and EM11D
20 processors. ARC EM Enhanced Security Package (ESP) and ARC EM
/Zephyr-latest/soc/snps/emsdp/
DKconfig.soc11 Synopsys ARC EM4 of EMSDP
17 Synopsys ARC EM5D of EMSDP
23 Synopsys ARC EM6 of EMSDP
29 Synopsys ARC EM7D of EMSDP
35 Synopsys ARC EM7D+ESP of EMSDP
41 Synopsys ARC EM9D of EMSDP
47 Synopsys ARC EM11D of EMSDP
/Zephyr-latest/arch/arc/core/mpu/
DKconfig7 int "ARC MPU version"
11 ARC MPU has several versions. For MPU v2, the minimum region is 2048 bytes;
16 bool "ARC Core MPU functionalities"
18 ARC core MPU functionalities
24 Enable thread stack guards via MPU. ARC supports built-in stack protection.
30 bool "ARC MPU Support"
41 Target has ARC MPU
/Zephyr-latest/doc/develop/toolchains/
Ddesignware_arc_mwdt.rst3 DesignWare ARC MetaWare Development Toolkit (MWDT)
6 #. You need to have `ARC MWDT <https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware>`_ installed on
13 Even though ARC MWDT toolchain is used for Zephyr RTOS build, still the GNU preprocessor & GNU
15 generation. We used Zephyr SDK as a source of these ARC GNU tools as well.
16 … To setup ARC GNU toolchain please use SDK Bundle (Full or Minimal) instead of manual installation
28 If you have only one ARC MWDT toolchain version installed on your machine you may skip setting
41 /home/you/ARC/MWDT_2023.03/
47 C:\ARC\MWDT_2023.03\
/Zephyr-latest/boards/snps/hsdk4xd/
DKconfig.hsdk4xd1 # DesignWare ARC HSDK4XD Development Kit board configuration
9 The ARC HS4x/4xD Development Kit is a ready-to-use software development
10 platform for the ARC HS4x/4xD family of processor IP. It includes
11 a multicore ARC HS4x/HS4xD-based chip and integrates a wide range
/Zephyr-latest/boards/snps/hsdk/
DKconfig.hsdk1 # DesignWare ARC HS Development Kit board configuration
9 The DesignWare ARC HS Development Kit is a ready-to-use platform for
10 rapid software development on the ARC HS3x family of processors. It
11 supports single- and multi-core ARC HS34, HS36 and HS38 processors
/Zephyr-latest/tests/arch/arc/arc_vpx_lock/
DREADME.txt1 Title: ARC VPX Lock
5 This test verifies that the ARC VPX lock/unlock mechanism used to bookend
6 code that uses the ARC VPX vector registers works correctly. As this VPX
11 However, it does check that the system behaves as expected when the ARC VPX
/Zephyr-latest/soc/snps/emsk/
DKconfig.soc8 Synopsys ARC EM Starter Kit SoC
14 Synopsys ARC EM7D of EMSK
20 Synopsys ARC EM9D of EMSK
26 Synopsys ARC EM11D of EMSK
/Zephyr-latest/drivers/timer/
DKconfig.arcv27 bool "ARC Timer"
9 depends on ARC
16 int "ARC timer interrupt priority"
20 This option specifies the IRQ priority used by the ARC timer. Lower
/Zephyr-latest/boards/snps/nsim/arc_v/
Dboard.cmake8 board_set_flasher_ifnset(arc-nsim)
9 board_set_debugger_ifnset(arc-nsim)
12 board_runner_args(arc-nsim "--props=${NSIM_PROPS}")
14 board_finalize_runner_args(arc-nsim)
/Zephyr-latest/arch/arc/core/dsp/
DKconfig6 menu "ARC DSP Options"
30 bool "ARC complex DSP operation"
39 bool "ARC address generation unit registers"
45 bool "ARC address generation unit register sharing"
56 bool "ARC AGU medium size register"
63 bool "ARC AGU large size register"
/Zephyr-latest/boards/snps/nsim/arc_classic/
DKconfig.nsim1 # DesignWare ARC nSIM simulated platform configuration
26 The DesignWare ARC nSIM board is a virtual board based on
27 the ARC nSIM simulator. It demonstrates the ARC core features
Dboard.cmake8 board_set_flasher_ifnset(arc-nsim)
9 board_set_debugger_ifnset(arc-nsim)
12 board_runner_args(arc-nsim "--props=${NSIM_PROPS}")
20 board_finalize_runner_args(arc-nsim)
/Zephyr-latest/boards/snps/hsdk/support/
Dopenocd.cfg30 # Contains quad-core ARC HS38.
33 source [find cpu/arc/hs.tcl]
40 set _CHIPNAME arc-em
54 # ARC HS38 core 2
66 $_TARGETNAME2 arc cache l2 auto 1
69 # ARC HS38 core 3
81 $_TARGETNAME3 arc cache l2 auto 1
84 # ARC HS38 core 4
97 $_TARGETNAME4 arc cache l2 auto 1
100 # ARC HS38 core 1
[all …]
Dopenocd-2-cores.cfg30 # Contains quad-core ARC HS38.
33 source [find cpu/arc/hs.tcl]
40 set _CHIPNAME arc-em
54 # ARC HS38 core 2
66 $_TARGETNAME2 arc cache l2 auto 1
69 # ARC HS38 core 1
81 $_TARGETNAME1 arc cache l2 auto 1
/Zephyr-latest/boards/snps/hsdk4xd/support/
Dopenocd.cfg30 # Contains quad-core ARC HS4x.
33 source [find cpu/arc/hs.tcl]
40 set _CHIPNAME arc-em
54 # ARC HS4x core 2
66 $_TARGETNAME2 arc cache l2 auto 1
69 # ARC HS4x core 3
81 $_TARGETNAME3 arc cache l2 auto 1
84 # ARC HS4x core 4
97 $_TARGETNAME4 arc cache l2 auto 1
100 # ARC HS4x core 1
[all …]
/Zephyr-latest/include/zephyr/arch/arc/v2/
Derror.h11 * ARC-specific kernel error handling interface. Included by arc/arch.h.
17 #include <zephyr/arch/arc/syscall.h>
18 #include <zephyr/arch/arc/v2/exception.h>
/Zephyr-latest/boards/snps/nsim/arc_classic/doc/
Dindex.rst6 This platform can be used to run Zephyr RTOS on the widest possible range of ARC processors in
7 simulation with `Designware ARC nSIM`_ or run same images on FPGA prototyping platform `HAPS`_. The
10 * ARC processor core, which implements ARCv2 or ARCv3 ISA, please refer to
11 :ref:`here <hardware_arch_arc_support_status>` for a complete list of ARC processor families which
15 ARC processors are known for being highly customizable and some but not all of the configurations
16 are currently supported in the Zephyr RTOS for ARC, again please refer to
22 * ``nsim/nsim_em`` - ARC EM core v4.0 with two register banks, FastIRQ's, MPUv2, DSP options and
24 * ``nsim/nsim_em7d_v22`` - ARC EM core v3.0 with one register bank and FastIRQ's
25 * ``nsim/nsim_em11d`` - ARC EM core v4.0 with one register bank, no FastIRQ's, MPUv2, DSP options a…
27 * ``nsim/nsim_sem`` - ARC EM core v4.0 with secure features (thus "SEM", i.e. Secure EM) and MPUv4
[all …]
/Zephyr-latest/boards/snps/em_starterkit/
Dem_starterkit_emsk_em11d.dts31 compatible = "arc,iccm";
36 compatible = "arc,dccm";
41 compatible = "arc,xccm";
46 compatible = "arc,yccm";
Dem_starterkit_emsk_em9d.dts31 compatible = "arc,iccm";
36 compatible = "arc,dccm";
41 compatible = "arc,xccm";
46 compatible = "arc,yccm";
/Zephyr-latest/boards/snps/iotdk/
DKconfig.iotdk1 # DesignWare ARC IoT Development Kit board configuration
9 The DesignWare ARC IoT Development Kit board is a versatile platform that includes the
12 implementation of the ARC Data Fusion IP Subsystem running at 144 MHz on SMIC's 55-nm
/Zephyr-latest/boards/snps/iotdk/doc/
Dindex.rst6 The DesignWare(R) ARC(R) IoT Development Kit is a versatile platform that
9 detection designs. The ARC IoT Development Kit includes a silicon
10 implementation of the ARC Data Fusion IP Subsystem running at 144 MHz on
14 For details about the board, see: `ARC IoT Development Kit
21 For hardware feature details, refer to : `ARC IoT Development Kit
22 <https://embarc.org/project/arc-iot-development-kit/>`__
47 Set up the ARC IoT Development Kit
72 ``iotdk`` as the board configuration, you can select the ARC IoT Development
147 $ $ZEPHYR_SDK_INSTALL_DIR/arc-zephyr-elf/bin/arc-zephyr-elf-gdb zephyr.elf
189 .. _Designware ARC IoT Development Kit website: https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_de…
/Zephyr-latest/dts/bindings/arc/
Darc,dccm.yaml4 description: ARC DCCM
6 compatible: "arc,dccm"
Darc,iccm.yaml4 description: ARC ICCM
6 compatible: "arc,iccm"

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