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/Zephyr-Core-3.5.0/soc/arm/arm/beetle/
Dsoc_registers.h33 /* Offset: 0x030 (r/w)APB peripheral access control set */
35 /* Offset: 0x034 (r/w)APB peripheral access control clear */
64 /* Offset: 0x0a0 (r/w) APB peripheral clock set in active state */
66 /* Offset: 0x0a4 (r/w) APB peripheral clock clear in active state */
68 /* Offset: 0x0a8 (r/w) APB peripheral clock set in sleep state */
70 /* Offset: 0x0ac (r/w) APB peripheral clock clear in sleep state */
72 /* Offset: 0x0b0 (r/w) APB peripheral clock set in deep sleep state */
74 /* Offset: 0x0b4 (r/w) APB peripheral clock clear in deep sleep state */
81 /* Offset: 0x0c8 (r/w) APB peripheral reset select set */
83 /* Offset: 0x0cc (r/w) APB peripheral reset select clear */
[all …]
Dpower.c68 /* Enable AHB and APB clocks */ in clock_active_init()
72 /* Configure APB Peripheral Clock in active state */ in clock_active_init()
83 /* Configure APB Peripheral Clock in sleep state */ in clock_sleep_init()
94 /* Configure APB Peripheral Clock in deep sleep state */ in clock_deepsleep_init()
Dsoc_pins.h28 /* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */
Dsoc.h38 /* Beetle SoC APB Devices */
71 /* Beetle SoC APB peripherals */
/Zephyr-Core-3.5.0/drivers/serial/
DKconfig.cmsdk_apb1 # ARM CMSDK APB SoC UART configuration options
7 bool "ARM CMSDK APB UART driver"
13 This option enables the UART driver for ARM CMSDK APB UART.
/Zephyr-Core-3.5.0/drivers/watchdog/
DKconfig.cmsdk_apb7 bool "CMSDK APB Watchdog Driver for ARM family of MCUs"
12 Enable CMSDK APB Watchdog (WDOG_CMSDK_APB) Driver for ARM
Dwdt_dw.h17 * The DW_apb_wdt is an APB slave peripheral that can be used to prevent system lockup that may be
214 * Width of the APB Data Bus to which this component is attached.
219 * APB data width is 8 bits
224 * APB data width is 16 bits
229 * APB data width is 32 bits
543 * @brief Width of the APB Data Bus to which this component is attached.
546 * @return APB data width
547 * 0x0 (APB_8BITS): APB data width is 8 bits
548 * 0x1 (APB_16BITS): APB data width is 16 bits
549 * 0x2 (APB_32BITS): APB data width is 32 bits
/Zephyr-Core-3.5.0/drivers/clock_control/
Dclock_control_gd32.c147 * Up to a certain threshold value of APB{1,2} prescaler, timer in clock_control_gd32_get_rate()
150 * threshold, timer clock is set to a multiple of the APB in clock_control_gd32_get_rate()
171 * If the APB prescaler equals 1, the timer clock frequencies in clock_control_gd32_get_rate()
172 * are set to the same frequency as that of the APB domain. in clock_control_gd32_get_rate()
173 * Otherwise, they are set to twice the frequency of the APB in clock_control_gd32_get_rate()
/Zephyr-Core-3.5.0/drivers/entropy/
Dentropy_esp32.c22 * of extra entropy from a hardware randomness source every APB clock cycle in entropy_esp32_get_u32()
24 * faster than it is added, this function needs to wait for at least 16 APB in entropy_esp32_get_u32()
/Zephyr-Core-3.5.0/boards/sparc/gr716a_mini/doc/
Dindex.rst96 AHB/APB Bridge Cobham Gaisler
97 AHB/APB Bridge Cobham Gaisler
98 AHB/APB Bridge Cobham Gaisler
99 AHB/APB Bridge Cobham Gaisler
102 AHB/APB Bridge Cobham Gaisler
/Zephyr-Core-3.5.0/dts/riscv/starfive/
Dstarfive_jh7100_beagle_v.dtsi138 compatible = "ns16550", "snps,dw-apb-uart";
151 compatible = "ns16550", "snps,dw-apb-uart";
164 compatible = "ns16550", "snps,dw-apb-uart";
177 compatible = "ns16550", "snps,dw-apb-uart";
/Zephyr-Core-3.5.0/samples/drivers/counter/maxim_ds3231/src/
Dmain.c85 void timespec_add(struct timespec *apb, in timespec_add() argument
89 apb->tv_nsec = a->tv_nsec + b->tv_nsec; in timespec_add()
90 apb->tv_sec = a->tv_sec + b->tv_sec; in timespec_add()
91 if (apb->tv_nsec >= NSEC_PER_SEC) { in timespec_add()
92 apb->tv_sec += 1; in timespec_add()
93 apb->tv_nsec -= NSEC_PER_SEC; in timespec_add()
/Zephyr-Core-3.5.0/soc/arm/atmel_sam0/common/
Dgmac_fixup_samd5x.h9 * APB-specific symbols, in order to accommodate different SoC series with the
/Zephyr-Core-3.5.0/dts/bindings/clock/
Dnuvoton,numaker-scc.yaml44 Configure APB Clock Divider register
Dst,stm32wba-rcc.yaml7 clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/interrupt-controller/
Desp32s2-xtensa-intmux.h90 #define PMS_DMA_APB_I_ILG_INTR_SOURCE 80 /* illegal APB access, level */
101 #define APB_ADC_INTR_SOURCE 89 /* APB ADC, level */
104 #define APB_PERI_ERROR_INTR_SOURCE 92 /* APB peripherals error, level */
/Zephyr-Core-3.5.0/dts/bindings/reset/
Dst,stm32-rcc-rctl.yaml7 and APB (Advanced Peripheral) bus domains.
/Zephyr-Core-3.5.0/dts/bindings/counter/
Despressif,esp32-timer.yaml46 The prescaler value defines the factor by which the APB clock will be
/Zephyr-Core-3.5.0/soc/arc/snps_arc_iot/
Dsysconf.h20 volatile uint32_t APBCLKDIV; /* APB clock divisor */
21 volatile uint32_t APBCLKEN; /* APB module clock enable */
/Zephyr-Core-3.5.0/drivers/counter/
Dcounter_dw_timer.c20 /* DW APB timer register offsets */
30 /* DW APB timer control flags */
35 /* DW APB timer modes */
Dcounter_ll_stm32_timer.c424 * Up to a certain threshold value of APB{1,2} prescaler, timer clock in counter_stm32_get_tim_clk()
427 * to a multiple of the APB domain clock PCLK{1,2} (2 if TIMPRE=0, 4 if in counter_stm32_get_tim_clk()
454 * If the APB prescaler equals 1, the timer clock frequencies in counter_stm32_get_tim_clk()
455 * are set to the same frequency as that of the APB domain. in counter_stm32_get_tim_clk()
457 * APB domain. in counter_stm32_get_tim_clk()
/Zephyr-Core-3.5.0/soc/arm/nuvoton_npcx/common/
Dsoc_clock.h114 /* Get APB clock freq */
115 #define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
/Zephyr-Core-3.5.0/drivers/pwm/
Dpwm_npcx.c68 /* Select APB CLK/LFCLK clock sources to PWM module by default */ in pwm_npcx_configure()
72 /* Select clock source to LFCLK by flag, otherwise APB clock source */ in pwm_npcx_configure()
/Zephyr-Core-3.5.0/dts/arm64/fvp/
Dfvp-aemv8r.dtsi53 uartclk: apb-pclk {
/Zephyr-Core-3.5.0/dts/arm/intel_socfpga_std/
Dsocfpga.dtsi118 compatible = "ns16550","snps,dw-apb-uart";
127 compatible = "ns16550","snps,dw-apb-uart";

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