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/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/
Dtest_stm32_clock_configuration_adc.c13 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(adc1))
59 static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(adc1)); in ZTEST()
69 "ADC1 gating clock should be off initially"); in ZTEST()
74 zassert_true((r == 0), "Could not enable ADC1 gating clock"); in ZTEST()
77 zassert_true(ADC_IS_CLK_ENABLED(), "[HAL] ADC1 gating clock should be on"); in ZTEST()
81 "[Zephyr] ADC1 gating clock should be on"); in ZTEST()
82 TC_PRINT("ADC1 gating clock on\n"); in ZTEST()
84 if (IS_ENABLED(STM32_ADC_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(adc1)) > 1) { in ZTEST()
89 zassert_true((r == 0), "Could not enable ADC1 domain clock"); in ZTEST()
90 TC_PRINT("ADC1 source clock configured\n"); in ZTEST()
[all …]
/Zephyr-latest/samples/drivers/adc/adc_dt/boards/
Dmimxrt1040_evk.overlay10 io-channels = <&adc1 3>, <&adc1 4>;
14 &adc1 {
20 * J33.1 (ADC1 CH3) and J33.2 (ADC1 CH4) to voltages between 0 and 3.3V
Dnucleo_c031c6.overlay10 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 4>;
14 &adc1 {
Darduino_opta_stm32h747xx_m7.overlay11 <&adc1 0>, /* I1 */
13 <&adc1 6>, /* I3 */
22 &adc1 {
/Zephyr-latest/tests/drivers/adc/adc_api/boards/
Dmimxrt1040_evk.overlay10 io-channels = <&adc1 3>, <&adc1 4>;
14 &adc1 {
20 * J33.1 (ADC1 CH3) and J33.2 (ADC1 CH4) to voltages between 0 and 3.3V
Dnucleo_wb05kz.overlay9 io-channels = <&adc1 4>, <&adc1 12>, <&adc1 13>;
13 &adc1 {
Dnucleo_wb09ke.overlay9 io-channels = <&adc1 4>, <&adc1 12>, <&adc1 13>;
13 &adc1 {
Dnucleo_f722ze.overlay9 io-channels = <&adc1 3>, <&adc1 10>;
13 &adc1 {
Dmimxrt1010_evk.overlay11 io-channels = <&adc1 0>, <&adc1 1>;
15 &adc1 {
Dmimxrt1015_evk.overlay11 io-channels = <&adc1 0>, <&adc1 1>;
15 &adc1 {
Dmimxrt1020_evk.overlay11 io-channels = <&adc1 0>, <&adc1 1>;
15 &adc1 {
Dmimxrt1024_evk.overlay11 io-channels = <&adc1 0>, <&adc1 1>;
15 &adc1 {
Dmimxrt1050_evk_mimxrt1052_hyperflash.overlay11 io-channels = <&adc1 0>, <&adc1 1>;
15 &adc1 {
Dmimxrt1050_evk_qspi.overlay11 io-channels = <&adc1 0>, <&adc1 1>;
15 &adc1 {
Dmimxrt1060_evk_mimxrt1062_qspi.overlay11 io-channels = <&adc1 0>, <&adc1 1>;
15 &adc1 {
Dmimxrt1060_evk_mimxrt1062_qspi_B.overlay11 io-channels = <&adc1 0>, <&adc1 1>;
15 &adc1 {
Dmimxrt1062_fmurt6.overlay11 io-channels = <&adc1 0>, <&adc1 1>;
15 &adc1 {
Dmimxrt1064_evk.overlay11 io-channels = <&adc1 0>, <&adc1 1>;
15 &adc1 {
Dnucleo_h753zi.overlay10 io-channels = <&adc1 12>, <&adc1 15>;
14 &adc1 {
Dstm32u083c_dk.overlay10 io-channels = <&adc1 0>, <&adc1 1>;
14 &adc1 {
Dnucleo_h7a3zi_q.overlay10 io-channels = <&adc1 12>, <&adc1 15>;
14 &adc1 {
Dstm32l562e_dk.overlay10 io-channels = <&adc1 13>, <&adc1 14>;
14 &adc1 {
Dnucleo_l552ze_q.overlay10 io-channels = <&adc1 1>, <&adc1 2>;
14 &adc1 {
/Zephyr-latest/samples/drivers/adc/adc_sequence/boards/
Dmimxrt1040_evk.overlay9 adc0 = &adc1;
13 &adc1 {
19 * J33.1 (ADC1 CH3) and J33.2 (ADC1 CH4) to voltages between 0 and 3.3V
/Zephyr-latest/dts/bindings/adc/
Dgd,gd32-adc.yaml8 # 2. adc0 and adc1 share the same irq number.
9 # 3. For gd32f4xx, adc2 share the same irq number with adc0 and adc1.
11 # To cover this cases, adc_gd32 driver use node-label 'adc0', 'adc1' and
15 # 'adc1' and 'adc2'.

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