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/Zephyr-latest/arch/xtensa/core/
Dsyscall_helper.c21 register uintptr_t a6 __asm__("%a6") = arg1; in xtensa_syscall_helper_args_6()
30 : "r" (a2), "r" (a6), "r" (a3), "r" (a4), in xtensa_syscall_helper_args_6()
42 register uintptr_t a6 __asm__("%a6") = arg1; in xtensa_syscall_helper_args_5()
50 : "r" (a2), "r" (a6), "r" (a3), "r" (a4), in xtensa_syscall_helper_args_5()
62 register uintptr_t a6 __asm__("%a6") = arg1; in xtensa_syscall_helper_args_4()
69 : "r" (a2), "r" (a6), "r" (a3), "r" (a4), in xtensa_syscall_helper_args_4()
80 register uintptr_t a6 __asm__("%a6") = arg1; in xtensa_syscall_helper_args_3()
86 : "r" (a2), "r" (a6), "r" (a3), "r" (a4) in xtensa_syscall_helper_args_3()
96 register uintptr_t a6 __asm__("%a6") = arg1; in xtensa_syscall_helper_args_2()
101 : "r" (a2), "r" (a6), "r" (a3) in xtensa_syscall_helper_args_2()
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Ddebug_helpers_asm.S24 * Use a6 and a7 as scratch */
27 l32i a6, a5, 0
29 l32i a7, a6, ___xtensa_irq_bsa_t_pc_OFFSET
33 l32i a7, a6, ___xtensa_irq_bsa_t_a0_OFFSET
37 addi a6, a6, ___xtensa_irq_bsa_t_SIZEOF
39 s32i a6, a3, 0
Dcrt1.S37 # define ARG5 a6 /* 5th outgoing call argument */
41 # define ARG1 a6 /* 1st outgoing call argument */
156 * a6 = pointer to start of table, and through table
162 movi a6, _bss_table_start
164 bgeu a6, a7, .L3zte
166 .L0zte: l32i a8, a6, 0 /* get start address, assumed multiple of 4 */
167 l32i a9, a6, 4 /* get end address, assumed multiple of 4 */
168 addi a6, a6, 8 /* next entry */
186 bltu a6, a7, .L0zte /* loop until end of table of *.bss sections */
Duserspace.S18 * a2 a6, a3, a4, a5, a8, a9
162 * arg1 = a6
205 s32i a6, a3, ___xtensa_irq_bsa_t_a2_OFFSET
295 s32i a6, a1, 4
298 l32i a6, a1, 24
301 l32i a6, a1, 24
324 * call, so parameters start at a6, a7, ...
326 l32i a6, a1, 20
Dwindow_vectors.S141 s32e a6, a0, -24 /* save a6 to call[j]'s stack frame */
170 l32e a6, a7, -24 /* restore a6 from call[i]'s stack frame */
199 s32e a6, a0, -40 /* save a6 to end of call[j]'s stack frame */
232 l32e a6, a11, -40 /* restore a6 from end of call[i]'s stack frame */
Dthread.c104 /* Arguments to z_thread_entry(). Remember these start at A6, in init_stack()
110 frame->a6 = (uintptr_t)entry; /* a6 */ in init_stack()
Dxtensa_asm2_util.S64 s32i a6, a1, 8
111 l32i a6, a2, 8
287 rsr a6, ZSR_CPU
288 l32i a6, a6, ___cpu_t_current_OFFSET
/Zephyr-latest/include/zephyr/arch/xtensa/
Dsyscall.h57 * a2 a6, a3, a4, a5, a8, a9
71 register uintptr_t a6 __asm__("%a6") = arg1; in arch_syscall_invoke6()
80 : "r" (a2), "r" (a6), "r" (a3), "r" (a4), in arch_syscall_invoke6()
96 register uintptr_t a6 __asm__("%a6") = arg1; in arch_syscall_invoke5()
104 : "r" (a2), "r" (a6), "r" (a3), "r" (a4), in arch_syscall_invoke5()
120 register uintptr_t a6 __asm__("%a6") = arg1; in arch_syscall_invoke4()
127 : "r" (a2), "r" (a6), "r" (a3), "r" (a4), in arch_syscall_invoke4()
139 register uintptr_t a6 __asm__("%a6") = arg1; in arch_syscall_invoke3()
145 : "r" (a2), "r" (a6), "r" (a3), "r" (a4) in arch_syscall_invoke3()
155 register uintptr_t a6 __asm__("%a6") = arg1; in arch_syscall_invoke2()
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/Zephyr-latest/include/zephyr/arch/arm64/
Darm-smccc.h21 unsigned long a6; member
43 unsigned long a6, unsigned long a7,
56 unsigned long a6, unsigned long a7,
/Zephyr-latest/dts/bindings/gpio/
Darduino-mkr-header.yaml10 A1 to A6 is Analog input. The outside pin is AREF.
19 correspond to A0 through A6, as depicted below.
28 21 A6/D21 D12/SCL 12
Dsparkfun-pro-micro-header.yaml25 4 D4/A6 D19/A1 19
Darduino-nano-header-r3.yaml24 3 D3 A6/D20 20
/Zephyr-latest/tests/drivers/tee/optee/src/
Dmain.c33 unsigned long a4, unsigned long a5, unsigned long a6, unsigned long a7,
46 uint32_t a6; member
55 unsigned long a4, unsigned long a5, unsigned long a6, unsigned long a7, in arm_smccc_smc() argument
75 t_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
78 wait_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
81 send_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
87 unsigned long a4, unsigned long a5, unsigned long a6, unsigned long a7, in arm_smccc_hvc() argument
115 unsigned long a4, unsigned long a5, unsigned long a6, unsigned long a7, in fast_call() argument
124 t_call.a6 = a6; in fast_call()
131 unsigned long a4, unsigned long a5, unsigned long a6, unsigned long a7, in fail_call() argument
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/Zephyr-latest/arch/riscv/core/
Dcoredump.c31 uint64_t a6; member
53 uint32_t a6;
106 arch_blk.r.a6 = esf->a6; in arch_coredump_info_dump()
/Zephyr-latest/arch/xtensa/include/
Dxtensa_asm2_context.h54 * - Saved A6 |
196 uintptr_t a6; member
217 uintptr_t a6; member
233 uintptr_t a6; member
Dxtensa_asm2_s.h356 mov a6, a3 /* place "new sp" in the next frame's A2 */
368 mov a2, a6 /* copy return value */
381 mov a2, a6 /* copy return value */
386 * handler pointer is still in A6 (not A2) even though this is
530 * to restore to in A6 (the call4'd function's A2). If this
537 beq a6, a1, _restore_\@
551 mov a1, a6
560 mov a2, a6
567 rsr a6, ZSR_CPU
568 l32i a6, a6, ___cpu_t_current_OFFSET
/Zephyr-latest/scripts/coredump/gdbstubs/arch/
Dxtensa.py290 A6 = 95 variable in GdbRegDef_Sample_Controller.RegNum
324 A6 = 163 variable in GdbRegDef_ESP32.RegNum
356 A6 = 161 variable in GdbRegDef_ESP32S2.RegNum
386 A6 = 218 variable in GdbRegDef_ESP32S3.RegNum
427 A6 = 164 variable in GdbRegDef_Intel_Adsp_CAVS_Zephyr.RegNum
467 A6 = 262 variable in GdbRegDef_Intel_Adsp_CAVS_XCC.RegNum
502 A6 = 111 variable in GdbRegDef_DC233C.RegNum
Drisc_v.py33 A6 = 16 variable in RegNum
89 self.registers[RegNum.A6] = tu[11]
/Zephyr-latest/include/zephyr/drivers/sip_svc/
Dsip_svc_driver.h73 unsigned long *a4, unsigned long *a5, unsigned long *a6,
263 * @param a6 Argument 6 for supervisory call.
272 unsigned long *a4, unsigned long *a5, unsigned long *a6,
277 unsigned long *a5, unsigned long *a6, in z_impl_sip_svc_plat_async_res_req() argument
291 __ASSERT(a6, "a6 shouldn't be NULL"); in z_impl_sip_svc_plat_async_res_req()
295 return api->sip_svc_plat_async_res_req(dev, a0, a1, a2, a3, a4, a5, a6, a7, buf, size); in z_impl_sip_svc_plat_async_res_req()
/Zephyr-latest/tests/arch/riscv/fatal/
Dtestcase.yaml21 - "E: a6: a6ff0000ff001016 t6: d6ff0000ff001f31"
/Zephyr-latest/drivers/sip_svc/
Dsip_smc_intel_socfpga.c119 unsigned long *a4, unsigned long *a5, unsigned long *a6, in intel_sip_smc_plat_async_res_req() argument
201 LOG_DBG("\tres->a6 %08lx", res->a6); in intel_sip_secure_monitor_call()
/Zephyr-latest/doc/develop/test/figures/
Dtwister_and_pytest.svg4 …a6" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-event…
/Zephyr-latest/boards/sparkfun/pro_micro_rp2040/
Dsparkfun_pro_micro_connector.dtsi18 , <4 0 &gpio0 4 0> /* D4/A6 */
/Zephyr-latest/boards/adafruit/kb2040/
Dsparkfun_pro_micro_connector.dtsi18 , <4 0 &gpio0 4 0> /* D4/A6 */
/Zephyr-latest/tests/lib/cmsis_dsp/common/
Dtest_common.h59 #define DEFINE_TEST_VARIANT6(suite, name, variant, a1, a2, a3, a4, a5, a6) \ argument
62 test_##name(a1, a2, a3, a4, a5, a6); \
65 #define DEFINE_TEST_VARIANT7(suite, name, variant, a1, a2, a3, a4, a5, a6, a7) \ argument
68 test_##name(a1, a2, a3, a4, a5, a6, a7); \

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