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/Zephyr-Core-3.5.0/arch/riscv/core/
Duserspace.S28 li a5, 0 # Counter
29 sw a5, 0(a2) # Init error value to 0
32 add a4, a0, a5 # Determine character address
38 bne a5, a1, continue # Check if max length is reached
41 mv a0, a5 # Return counter value (length)
45 addi a5, a5, 1 # Increment counter
Dcoredump.c24 uint32_t a5; member
72 arch_blk.r.a5 = esf->a5; in arch_coredump_info_dump()
Dfatal.c41 LOG_ERR(" a5: " PR_REG, esf->a5); in z_riscv_fatal_error()
45 LOG_ERR(" a5: " PR_REG " t5: " PR_REG, esf->a5, esf->t5); in z_riscv_fatal_error()
/Zephyr-Core-3.5.0/arch/xtensa/core/
Dwindow_vectors.S49 * a5 is call[j+1]'s stack pointer.
56 s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */
57 s32e a1, a5, -12 /* save a1 to call[j+1]'s stack frame */
58 s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */
59 s32e a3, a5, -4 /* save a3 to call[j+1]'s stack frame */
71 * a5 is call[i+1]'s stack pointer.
78 l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */
79 l32e a1, a5, -12 /* restore a1 from call[i+1]'s stack frame */
80 l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */
81 l32e a3, a5, -4 /* restore a3 from call[i+1]'s stack frame */
[all …]
/Zephyr-Core-3.5.0/include/zephyr/arch/arm64/
Darm-smccc.h20 unsigned long a5; member
42 unsigned long a4, unsigned long a5,
55 unsigned long a4, unsigned long a5,
/Zephyr-Core-3.5.0/tests/bluetooth/ctrl_sw_privacy_unit/src/
Dmain.c48 bt_addr_t a1, a2, a3, a4, a5; in helper_prpa_add() local
55 bt_addr_copy(&a5, BT_ADDR_INIT(0x52, 0x53, 0x54, 0x55, 0x56, 0x57)); in helper_prpa_add()
79 prpa_cache_add(&a5); in helper_prpa_add()
80 pos = prpa_cache_find(&a5); in helper_prpa_add()
91 bt_addr_t a1, a2, a3, a4, a5; in helper_trpa_add() local
98 bt_addr_copy(&a5, BT_ADDR_INIT(0x52, 0x53, 0x54, 0x55, 0x56, 0x57)); in helper_trpa_add()
122 trpa_cache_add(&a5, 4); in helper_trpa_add()
123 pos = trpa_cache_find(&a5, 4); in helper_trpa_add()
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Darduino-header-r3.yaml15 labeled from A0 at the top through A5 at the bottom.
24 through 5 correspond to A0 through A5, and parent pins 6 through 21
45 5 A5 D0 6
Dadafruit-feather-header.yaml16 through 5 correspond to A0 through A5, and parent pins 6 through 20
28 5 A5 D11 18
Dpanasonic,reduced-arduino-header.yaml25 NC A5 D0 6
36 2. Analog Input header, like on Arduino UNO layout, but A4 and A5 are
/Zephyr-Core-3.5.0/samples/drivers/spi_bitbang/
DREADME.rst39 wrote 0101 00ff 00a5 0000 0102
45 wrote 0101 00ff 00a5 0000 0102
51 wrote 0101 00ff 00a5 0000 0102
/Zephyr-Core-3.5.0/drivers/console/
Dwinstream_console.c30 register int a5 __asm__("a5") = len; in winstream_console_trace_out()
32 __asm__ volatile("simcall" : "+r"(a2), "+r"(a3) : "r"(a4), "r"(a5) : "memory"); in winstream_console_trace_out()
Dxtensa_sim_console.c23 register int a5 __asm__ ("a5") = 1; in console_out()
30 : "a" (a2), "a" (a3), "a" (a4), "a" (a5) in console_out()
/Zephyr-Core-3.5.0/arch/xtensa/core/startup/
Dreset-vector.S109 movi a5, CORE_STATE_SIGNATURE
118 sub a4, a4, a5
230 * effect, registers a3, a5, a7 are now preloaded with values
233 * a5 - saved state signature (CORE_STATE_SIGNATURE)
240 sub a4, a4, a5
249 addi a5, a7, - PWRSTAT_WAKEUP_RESET
251 movnez a7, a5, a4
412 extui a5, a8, 0, 2 /* lower two bit indicate whether cached */
415 moveqz a9, a10, a5 /* ... that region is non-cacheable */
416 addx4 a5, a8, a3 /* index into _xtos_mpu_attribs table */
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/Zephyr-Core-3.5.0/tests/drivers/i2c/i2c_target_api/boards/
Dnucleo_l476rg.overlay11 * i2c3 PC1 A4 PC0 A5
13 * Short D14 to A4, and D15 to A5, for the test to pass.
/Zephyr-Core-3.5.0/dts/bindings/adc/
Darduino,uno-adc.yaml8 has analog input signals labeled from A0 at the top through A5 at
12 pins 0 through 5 correspond to A0 through A5.
/Zephyr-Core-3.5.0/subsys/logging/backends/
Dlog_backend_xtensa_sim.c28 register int a5 __asm__ ("a5") = length; in char_out()
32 : "a"(a2), "a"(a3), "a"(a4), "a"(a5)); in char_out()
/Zephyr-Core-3.5.0/tests/lib/cmsis_dsp/common/
Dtest_common.h54 #define DEFINE_TEST_VARIANT5(suite, name, variant, a1, a2, a3, a4, a5) \ argument
57 test_##name(a1, a2, a3, a4, a5); \
60 #define DEFINE_TEST_VARIANT6(suite, name, variant, a1, a2, a3, a4, a5, a6) \ argument
63 test_##name(a1, a2, a3, a4, a5, a6); \
66 #define DEFINE_TEST_VARIANT7(suite, name, variant, a1, a2, a3, a4, a5, a6, a7) \ argument
69 test_##name(a1, a2, a3, a4, a5, a6, a7); \
96 #define DEFINE_TEST_VARIANT5(name, variant, a1, a2, a3, a4, a5) \ argument
99 test_##name(a1, a2, a3, a4, a5); \
102 #define DEFINE_TEST_VARIANT6(name, variant, a1, a2, a3, a4, a5, a6) \ argument
105 test_##name(a1, a2, a3, a4, a5, a6); \
[all …]
/Zephyr-Core-3.5.0/arch/xtensa/include/
Dxtensa-asm2-context.h50 * - Saved A5 +- If not in-use by another frame
178 uintptr_t a5; member
199 uintptr_t a5; member
215 uintptr_t a5; member
/Zephyr-Core-3.5.0/tests/drivers/gpio/gpio_basic_api/boards/
Dnucleo_f103rb.overlay11 in-gpios = <&arduino_header 5 0>; /* Arduino A5 */
Dnucleo_g071rb.overlay11 in-gpios = <&arduino_header 5 0>; /* Arduino A5 */
Dnucleo_l152re.overlay11 in-gpios = <&arduino_header 5 0>; /* Arduino A5 */
Dhifive1_revb.overlay11 in-gpios = <&gpio0 13 0>; /* Arduino A5 */
/Zephyr-Core-3.5.0/scripts/coredump/gdbstubs/arch/
Dxtensa.py289 A5 = 94 variable in GdbRegDef_Sample_Controller.RegNum
323 A5 = 162 variable in GdbRegDef_ESP32.RegNum
355 A5 = 160 variable in GdbRegDef_ESP32S2.RegNum
385 A5 = 217 variable in GdbRegDef_ESP32S3.RegNum
426 A5 = 163 variable in GdbRegDef_Intel_Adsp_CAVS_Zephyr.RegNum
466 A5 = 261 variable in GdbRegDef_Intel_Adsp_CAVS_XCC.RegNum
501 A5 = 110 variable in GdbRegDef_DC233C.RegNum
/Zephyr-Core-3.5.0/include/zephyr/arch/riscv/
Dsyscall.h49 register unsigned long a5 __asm__ ("a5") = arg6; in arch_syscall_invoke6()
54 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), in arch_syscall_invoke6()
/Zephyr-Core-3.5.0/include/zephyr/drivers/sip_svc/
Dsip_svc_driver.h73 unsigned long *a4, unsigned long *a5, unsigned long *a6,
262 * @param a5 Argument 5 for supervisory call.
272 unsigned long *a4, unsigned long *a5, unsigned long *a6,
277 unsigned long *a5, unsigned long *a6, in z_impl_sip_svc_plat_async_res_req() argument
290 __ASSERT(a5, "a5 shouldn't be NULL"); in z_impl_sip_svc_plat_async_res_req()
295 return api->sip_svc_plat_async_res_req(dev, a0, a1, a2, a3, a4, a5, a6, a7, buf, size); in z_impl_sip_svc_plat_async_res_req()

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