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/Zephyr-Core-3.5.0/arch/riscv/core/
Duserspace.S32 add a4, a0, a5 # Determine character address
34 lbu a4, 0(a4) # Load string's character
36 beqz a4, exit # Test string's end of line
49 li a4, -1 # Put error to -1
50 sw a4, 0(a2)
Dcoredump.c23 uint32_t a4; member
71 arch_blk.r.a4 = esf->a4; in arch_coredump_info_dump()
Dfatal.c40 LOG_ERR(" a4: " PR_REG, esf->a4); in z_riscv_fatal_error()
44 LOG_ERR(" a4: " PR_REG " t4: " PR_REG, esf->a4, esf->t4); in z_riscv_fatal_error()
/Zephyr-Core-3.5.0/arch/xtensa/core/
Dwindow_vectors.S42 * Invoked if a call[i] referenced a register (a4-a15)
48 * a4-a15 must be preserved;
70 * a4-a15 must be preserved (they are call[i+1].reg[0..11]);
101 rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratch */
104 xor a3, a3, a4 /* bits changed from old to current windowbase */
105 rsr a4, ZSR_ALLOCA /* restore original a0 (now in a4) */
111 _bbci.l a4, 31, _WindowUnderflow4
119 * Invoked if a call[i] referenced a register (a4-a15)
139 s32e a4, a0, -32 /* save a4 to call[j]'s stack frame */
168 l32e a4, a7, -32 /* restore a4 from call[i]'s stack frame */
[all …]
Ddebug_helpers_asm.S23 /* a2, a3, a4 should be out arguments for i PC, i SP, i-1 PC respectively.
34 /* Store value of (i-1) PC in a4 */
35 s32i a7, a4, 0
Dxtensa_backtrace.c99 __asm__ volatile("l32i a4, a3, 0"); in z_xtensa_backtrace_print()
100 __asm__ volatile("l32i a4, a4, 4"); in z_xtensa_backtrace_print()
101 __asm__ volatile("mov %0, a4" : "=r"(cause)); in z_xtensa_backtrace_print()
Dcrt1.S40 # define ARG3 a4 /* 3rd outgoing call argument */
143 movi a4, __memmap_init
144 beqz a4, 1f
145 CALLX a4
/Zephyr-Core-3.5.0/tests/lib/cmsis_dsp/common/
Dtest_common.h48 #define DEFINE_TEST_VARIANT4(suite, name, variant, a1, a2, a3, a4) \ argument
51 test_##name(a1, a2, a3, a4); \
54 #define DEFINE_TEST_VARIANT5(suite, name, variant, a1, a2, a3, a4, a5) \ argument
57 test_##name(a1, a2, a3, a4, a5); \
60 #define DEFINE_TEST_VARIANT6(suite, name, variant, a1, a2, a3, a4, a5, a6) \ argument
63 test_##name(a1, a2, a3, a4, a5, a6); \
66 #define DEFINE_TEST_VARIANT7(suite, name, variant, a1, a2, a3, a4, a5, a6, a7) \ argument
69 test_##name(a1, a2, a3, a4, a5, a6, a7); \
90 #define DEFINE_TEST_VARIANT4(name, variant, a1, a2, a3, a4) \ argument
93 test_##name(a1, a2, a3, a4); \
[all …]
/Zephyr-Core-3.5.0/include/zephyr/arch/arm64/
Darm-smccc.h19 unsigned long a4; member
42 unsigned long a4, unsigned long a5,
55 unsigned long a4, unsigned long a5,
/Zephyr-Core-3.5.0/arch/xtensa/core/startup/
Dreset-vector.S113 extui a4, a7, 1, 2
114 /* a4==1 means PSO wakeup, caches did not lose power */
115 bnei a4, 1, .Lcold_start
117 l32i a4, a3, CS_SA_signature
118 sub a4, a4, a5
120 bnez a4, .Lcold_start
123 l32i a4, a3, CS_SA_memctl
126 and a0, a4, a0
238 l32i a4, a3, CS_SA_signature
240 sub a4, a4, a5
[all …]
/Zephyr-Core-3.5.0/tests/bluetooth/ctrl_sw_privacy_unit/src/
Dmain.c48 bt_addr_t a1, a2, a3, a4, a5; in helper_prpa_add() local
54 bt_addr_copy(&a4, BT_ADDR_INIT(0x42, 0x43, 0x44, 0x45, 0x46, 0x47)); in helper_prpa_add()
73 prpa_cache_add(&a4); in helper_prpa_add()
74 pos = prpa_cache_find(&a4); in helper_prpa_add()
91 bt_addr_t a1, a2, a3, a4, a5; in helper_trpa_add() local
97 bt_addr_copy(&a4, BT_ADDR_INIT(0x42, 0x43, 0x44, 0x45, 0x46, 0x47)); in helper_trpa_add()
116 trpa_cache_add(&a4, 3); in helper_trpa_add()
117 pos = trpa_cache_find(&a4, 3); in helper_trpa_add()
/Zephyr-Core-3.5.0/include/zephyr/arch/riscv/
Dsyscall.h48 register unsigned long a4 __asm__ ("a4") = arg5; in arch_syscall_invoke6()
54 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), in arch_syscall_invoke6()
69 register unsigned long a4 __asm__ ("a4") = arg5; in arch_syscall_invoke5()
74 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (t0) in arch_syscall_invoke5()
/Zephyr-Core-3.5.0/drivers/console/
Dwinstream_console.c29 register int a4 __asm__("a4") = (int)str; in winstream_console_trace_out()
32 __asm__ volatile("simcall" : "+r"(a2), "+r"(a3) : "r"(a4), "r"(a5) : "memory"); in winstream_console_trace_out()
Dxtensa_sim_console.c22 register char *a4 __asm__ ("a4") = buf; in console_out()
30 : "a" (a2), "a" (a3), "a" (a4), "a" (a5) in console_out()
/Zephyr-Core-3.5.0/tests/drivers/i2c/i2c_target_api/boards/
Dnucleo_l476rg.overlay11 * i2c3 PC1 A4 PC0 A5
13 * Short D14 to A4, and D15 to A5, for the test to pass.
/Zephyr-Core-3.5.0/subsys/logging/backends/
Dlog_backend_xtensa_sim.c27 register int a4 __asm__ ("a4") = (int) data; in char_out()
32 : "a"(a2), "a"(a3), "a"(a4), "a"(a5)); in char_out()
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dpanasonic,reduced-arduino-header.yaml24 NC A4 D1 7
36 2. Analog Input header, like on Arduino UNO layout, but A4 and A5 are
/Zephyr-Core-3.5.0/samples/arch/mpu/mpu_test/
DREADME.rst56 <err> os: r3/a4: 0x24000000 r12/ip: 0x00000000 r14/lr: 0x000029b7
72 <err> os: r3/a4: 0x00004000 r12/ip: 0x00000004 r14/lr: 0x000003ab
86 <err> os: r3/a4: 0x20000000 r12/ip: 0x00000000 r14/lr: 0x00006673
114 <err> os: r3/a4: 0x24000000 r12/ip: 0x00000040 r14/lr: 0x0800d
127 <err> os: r3/a4: 0x0badc0de r12/ip: 0x00000000 r14/lr: 0x08009
/Zephyr-Core-3.5.0/tests/arch/arm/arm_interrupt/
DREADME.txt62 E: r3/a4: 0x00003109 r12/ip: 0xfabf33ff r14/lr: 0x00003e7f
76 E: r3/a4: 0x20001e40 r12/ip: 0x00000000 r14/lr: 0x00002f47
85 E: r3/a4: 0x20001e40 r12/ip: 0x00000000 r14/lr: 0x00002f47
97 E: r3/a4: 0x00000054 r12/ip: 0x00000000 r14/lr: 0x00002f47
109 E: r3/a4: 0x0000000f r12/ip: 0x00000000 r14/lr: 0xfffffff1
120 E: r3/a4: 0x01000000 r12/ip: 0xdfcdaf37 r14/lr: 0xe4698510
133 E: r3/a4: 0x00000003 r12/ip: 0x0000000c r14/lr: 0x0000000f
/Zephyr-Core-3.5.0/arch/xtensa/include/
Dxtensa-asm2-context.h51 * - Saved A4 /
177 uintptr_t a4; member
198 uintptr_t a4; member
214 uintptr_t a4; member
/Zephyr-Core-3.5.0/tests/drivers/gpio/gpio_basic_api/boards/
Dnucleo_f103rb.overlay10 out-gpios = <&arduino_header 4 0>; /* Arduino A4 */
Dnucleo_g071rb.overlay10 out-gpios = <&arduino_header 4 0>; /* Arduino A4 */
Dnucleo_l152re.overlay10 out-gpios = <&arduino_header 4 0>; /* Arduino A4 */
Dhifive1_revb.overlay10 out-gpios = <&gpio0 12 0>; /* Arduino A4 */
/Zephyr-Core-3.5.0/scripts/coredump/gdbstubs/arch/
Dxtensa.py288 A4 = 93 variable in GdbRegDef_Sample_Controller.RegNum
322 A4 = 161 variable in GdbRegDef_ESP32.RegNum
354 A4 = 159 variable in GdbRegDef_ESP32S2.RegNum
384 A4 = 216 variable in GdbRegDef_ESP32S3.RegNum
425 A4 = 162 variable in GdbRegDef_Intel_Adsp_CAVS_Zephyr.RegNum
465 A4 = 260 variable in GdbRegDef_Intel_Adsp_CAVS_XCC.RegNum
500 A4 = 109 variable in GdbRegDef_DC233C.RegNum

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