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/Zephyr-Core-3.5.0/boards/shields/x_nucleo_iks01a3/boards/x_nucleo_iks01a3/
Dstm32mp157c_dk2.overlay8 * On stm32mp157c_dk2 pin A3 is not mapped on a GPIO pin.
14 /delete-property/ irq-gpios; /* A3 */
18 /delete-property/ irq-gpios; /* A3 */
22 /delete-property/ irq-gpios; /* A3 */
/Zephyr-Core-3.5.0/arch/xtensa/core/
Dxtensa-asm2-util.S32 * Call with CALL0, with A2/A3 available as scratch. Pushes the high
46 slli a3, a2, (XCHAL_NUM_AREGS / 4)
47 or a2, a2, a3
48 rsr a3, WINDOWBASE
49 ssr a3
52 mov a3, a1 /* Stash our original stack pointer */
87 s32i a3, a1, 0
97 * CALL0, leaving A2/A3 available as scratch.
102 /* pop our "original" stack pointer into a2, stash in a3 also */
105 mov a3, a2
[all …]
Dwindow_vectors.S47 * a0-a3 are registers to be saved;
59 s32e a3, a5, -4 /* save a3 to call[j+1]'s stack frame */
69 * a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
81 l32e a3, a5, -4 /* restore a3 from call[i+1]'s stack frame */
101 rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratch */
103 extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
104 xor a3, a3, a4 /* bits changed from old to current windowbase */
106 slli a3, a3, XCHAL_PS_OWB_SHIFT
107 xor a2, a2, a3 /* flip changed bits in old window base */
138 s32e a3, a9, -4 /* save a3 to call[j+1]'s stack frame */
[all …]
Ddebug_helpers_asm.S23 /* a2, a3, a4 should be out arguments for i PC, i SP, i-1 PC respectively.
38 /* Store i SP in a3 */
39 s32i a6, a3, 0
DREADME-WINDOWS.rst15 The first quad (A0-A3) is pointed to by a special register called
18 (respectively) A0-A3, A4-A7, A8-A11, and A12-A15.
61 being brought into A0-A3 (i.e. the new WINDOWBASE) has a set bit
86 The spill area for a single frame's A0-A3 registers is not in its own
101 to write a function using only A0-A3 and CALL4 calls and ignore higher
103 the top of the stack frame, immediately below the parent call's A0-A3
Dcrt1.S39 # define ARG2 a3 /* 2nd outgoing call argument */
106 movi a3, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL)
114 movi a3, PS_UM|PS_WOE|PS_INTLEVEL(XCHAL_EXCM_LEVEL)
116 wsr a3, PS
/Zephyr-Core-3.5.0/boards/shields/x_nucleo_iks01a3/boards/x_nucleo_iks01a3_shub/
Dstm32mp157c_dk2.overlay8 * On stm32mp157c_dk2 pin A3 is not mapped on a GPIO pin.
14 /delete-property/ irq-gpios; /* A3 */
18 /delete-property/ irq-gpios; /* A3 */
/Zephyr-Core-3.5.0/arch/xtensa/include/
Dxtensa-asm2-s.h31 * and repeats until all but the A0-A3 registers of the original frame
156 * have been modified but A2/A3 have not, and the shift/loop
289 * (to save A0-A3) from registers. But they find their
340 * area) in A3. Exceptions should be enabled via PS.EXCM, but
344 * A2 has the return value of the called function, and A3 is
350 mov a6, a3 /* place "new sp" in the next frame's A2 */
352 mov a3, a1 /* stash it locally in A3 too */
353 mov a11, a2 /* handler in 2nd frame's A3, next frame's A7 */
361 mov a1, a3 /* restore original SP */
388 * the stack pointer decremented across a base save area, A0-A3 and
[all …]
Dxtensa-asm2-context.h18 * SP-4 Caller A3 spill slot \
23 * SP-20 Saved A3
84 * Note that only A0-A3 are saved here. High registers
131 uintptr_t a3; member
225 * Interrupt stack frame containing A0 - A3.
/Zephyr-Core-3.5.0/boards/shields/x_nucleo_iks01a2/boards/
Dstm32mp157c_dk2.overlay8 * On stm32mp157c_dk2 pin A3 is not mapped on a GPIO pin.
14 /delete-property/ irq-gpios; /* A3 */
18 /delete-property/ irq-gpios; /* A3 */
/Zephyr-Core-3.5.0/include/zephyr/arch/riscv/
Dsyscall.h47 register unsigned long a3 __asm__ ("a3") = arg4; in arch_syscall_invoke6()
54 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), in arch_syscall_invoke6()
68 register unsigned long a3 __asm__ ("a3") = arg4; in arch_syscall_invoke5()
74 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (t0) in arch_syscall_invoke5()
86 register unsigned long a3 __asm__ ("a3") = arg4; in arch_syscall_invoke4()
91 : "r" (a1), "r" (a2), "r" (a3), "r" (t0) in arch_syscall_invoke4()
/Zephyr-Core-3.5.0/arch/xtensa/core/startup/
Dreset-vector.S107 movi a3, _xtos_pso_savearea
117 l32i a4, a3, CS_SA_signature
123 l32i a4, a3, CS_SA_memctl
230 * effect, registers a3, a5, a7 are now preloaded with values
232 * a3 - pointer to save area base address (_xtos_pso_savearea)
238 l32i a4, a3, CS_SA_signature
273 rsr.prid a3 /* core and multiprocessor ID */
274 extui a3, a3, 0, 8 /* extract core ID (FIXME: need proper
277 bnez a3, .Ldonesync /* only do this on core 0 */
304 movi a3, 0x25
[all …]
/Zephyr-Core-3.5.0/tests/lib/cmsis_dsp/common/
Dtest_common.h42 #define DEFINE_TEST_VARIANT3(suite, name, variant, a1, a2, a3) \ argument
45 test_##name(a1, a2, a3); \
48 #define DEFINE_TEST_VARIANT4(suite, name, variant, a1, a2, a3, a4) \ argument
51 test_##name(a1, a2, a3, a4); \
54 #define DEFINE_TEST_VARIANT5(suite, name, variant, a1, a2, a3, a4, a5) \ argument
57 test_##name(a1, a2, a3, a4, a5); \
60 #define DEFINE_TEST_VARIANT6(suite, name, variant, a1, a2, a3, a4, a5, a6) \ argument
63 test_##name(a1, a2, a3, a4, a5, a6); \
66 #define DEFINE_TEST_VARIANT7(suite, name, variant, a1, a2, a3, a4, a5, a6, a7) \ argument
69 test_##name(a1, a2, a3, a4, a5, a6, a7); \
[all …]
/Zephyr-Core-3.5.0/subsys/logging/backends/
Dlog_backend_xtensa_sim.c26 register int a3 __asm__ ("a3") = 1; in char_out()
31 : "=a"(a2), "=a"(a3) in char_out()
32 : "a"(a2), "a"(a3), "a"(a4), "a"(a5)); in char_out()
/Zephyr-Core-3.5.0/drivers/console/
Dxtensa_sim_console.c21 register int a3 __asm__ ("a3") = 1; in console_out()
25 register int ret_err __asm__ ("a3"); in console_out()
30 : "a" (a2), "a" (a3), "a" (a4), "a" (a5) in console_out()
Dwinstream_console.c28 register int a3 __asm__("a3") = 1; /* fd 1 == stdout */ in winstream_console_trace_out()
32 __asm__ volatile("simcall" : "+r"(a2), "+r"(a3) : "r"(a4), "r"(a5) : "memory"); in winstream_console_trace_out()
/Zephyr-Core-3.5.0/include/zephyr/arch/arm64/
Darm-smccc.h18 unsigned long a3; member
41 unsigned long a2, unsigned long a3,
54 unsigned long a2, unsigned long a3,
/Zephyr-Core-3.5.0/tests/bluetooth/ctrl_sw_privacy_unit/src/
Dmain.c48 bt_addr_t a1, a2, a3, a4, a5; in helper_prpa_add() local
53 bt_addr_copy(&a3, BT_ADDR_INIT(0x32, 0x33, 0x34, 0x35, 0x36, 0x37)); in helper_prpa_add()
67 prpa_cache_add(&a3); in helper_prpa_add()
68 pos = prpa_cache_find(&a3); in helper_prpa_add()
91 bt_addr_t a1, a2, a3, a4, a5; in helper_trpa_add() local
96 bt_addr_copy(&a3, BT_ADDR_INIT(0x32, 0x33, 0x34, 0x35, 0x36, 0x37)); in helper_trpa_add()
110 trpa_cache_add(&a3, 2); in helper_trpa_add()
111 pos = trpa_cache_find(&a3, 2); in helper_trpa_add()
/Zephyr-Core-3.5.0/boards/shields/x_nucleo_iks01a2/
Dx_nucleo_iks01a2.overlay37 irq-gpios = <&arduino_header 3 GPIO_ACTIVE_HIGH>; /* A3 */
43 irq-gpios = <&arduino_header 3 GPIO_ACTIVE_HIGH>; /* A3 */
/Zephyr-Core-3.5.0/arch/riscv/core/
Dcoredump.c22 uint32_t a3; member
70 arch_blk.r.a3 = esf->a3; in arch_coredump_info_dump()
Dfatal.c39 LOG_ERR(" a3: " PR_REG, esf->a3); in z_riscv_fatal_error()
43 LOG_ERR(" a3: " PR_REG " t3: " PR_REG, esf->a3, esf->t3); in z_riscv_fatal_error()
/Zephyr-Core-3.5.0/samples/arch/mpu/mpu_test/
DREADME.rst55 <err> os: r0/a1: 0x00009a5c r1/a2: 0x00000008 r2/a3: 0x20001aa8
71 <err> os: r0/a1: 0x00000000 r1/a2: 0x0000000e r2/a3: 0x0badc0de
85 <err> os: r0/a1: 0x00009a5c r1/a2: 0x00000001 r2/a3: 0x20001aa8
113 <err> os: r0/a1: 0x0800a54c r1/a2: 0x00000008 r2/a3: 0x08003
126 <err> os: r0/a1: 0x00000000 r1/a2: 0x0000000e r2/a3: 0x0000e
/Zephyr-Core-3.5.0/tests/arch/arm/arm_interrupt/
DREADME.txt61 E: r0/a1: 0x20000000 r1/a2: 0x00000000 r2/a3: 0x20001e40
75 E: r0/a1: 0x00000003 r1/a2: 0x200020b8 r2/a3: 0x00000003
84 E: r0/a1: 0x00000004 r1/a2: 0x200020b8 r2/a3: 0x00000004
96 E: r0/a1: 0x00000004 r1/a2: 0x000000cf r2/a3: 0x00000000
108 E: r0/a1: 0x00000004 r1/a2: 0x00000017 r2/a3: 0x00000000
119 E: r0/a1: 0xdde8d9e7 r1/a2: 0x5510538d r2/a3: 0x00000d74
132 E: r0/a1: 0x00000000 r1/a2: 0x00000001 r2/a3: 0x00000002
/Zephyr-Core-3.5.0/scripts/coredump/gdbstubs/arch/
Dxtensa.py287 A3 = 92 variable in GdbRegDef_Sample_Controller.RegNum
321 A3 = 160 variable in GdbRegDef_ESP32.RegNum
353 A3 = 158 variable in GdbRegDef_ESP32S2.RegNum
383 A3 = 215 variable in GdbRegDef_ESP32S3.RegNum
424 A3 = 161 variable in GdbRegDef_Intel_Adsp_CAVS_Zephyr.RegNum
464 A3 = 259 variable in GdbRegDef_Intel_Adsp_CAVS_XCC.RegNum
499 A3 = 108 variable in GdbRegDef_DC233C.RegNum
/Zephyr-Core-3.5.0/drivers/sip_svc/
Dsip_smc_intel_socfpga.c118 unsigned long *a1, unsigned long *a2, unsigned long *a3, in intel_sip_smc_plat_async_res_req() argument
128 *a3 = size; in intel_sip_smc_plat_async_res_req()
198 LOG_DBG("\tres->a3 %08lx", res->a3); in intel_sip_secure_monitor_call()

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