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/Zephyr-latest/tests/arch/xtensa/save_restore_hifi/src/
Dhifi.S15 ae_s64.i aed0, a2, 0
16 ae_s64.i aed1, a2, 8
17 ae_s64.i aed2, a2, 16
18 ae_s64.i aed3, a2, 24
19 ae_s64.i aed4, a2, 32
20 ae_s64.i aed5, a2, 40
21 ae_s64.i aed6, a2, 48
22 ae_s64.i aed7, a2, 56
24 addi a2, a2, 64
26 ae_s64.i aed8, a2, 0
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/Zephyr-latest/arch/xtensa/core/
Dsyscall_helper.c20 register uintptr_t a2 __asm__("%a2") = call_id; in xtensa_syscall_helper_args_6()
29 : "=r" (a2) in xtensa_syscall_helper_args_6()
30 : "r" (a2), "r" (a6), "r" (a3), "r" (a4), in xtensa_syscall_helper_args_6()
34 return a2; in xtensa_syscall_helper_args_6()
41 register uintptr_t a2 __asm__("%a2") = call_id; in xtensa_syscall_helper_args_5()
49 : "=r" (a2) in xtensa_syscall_helper_args_5()
50 : "r" (a2), "r" (a6), "r" (a3), "r" (a4), in xtensa_syscall_helper_args_5()
54 return a2; in xtensa_syscall_helper_args_5()
61 register uintptr_t a2 __asm__("%a2") = call_id; in xtensa_syscall_helper_args_4()
68 : "=r" (a2) in xtensa_syscall_helper_args_4()
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Duserspace.S18 * a2 a6, a3, a4, a5, a8, a9
26 wsr a2, ZSR_SYSCALL_SCRATCH
30 rsr.epc1 a2
31 bne a0, a2, _not_checking_user_context
33 addi a2, a2, 3
34 wsr.epc1 a2
37 rsr.ps a2
38 and a2, a2, a0
44 beqz a2, _is_user_context_return
46 movi a2, 1
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Dxtensa_hifi.S20 * A2 - available for use
26 addi a2, a1, (___xtensa_irq_bsa_t_hifi_OFFSET + XCHAL_CP1_SA_ALIGN - 1)
28 and a2, a2, a3
30 xchal_cp1_load a2 a3 a3 a3 a3 /* Only A2 and A3 are used by macro */
41 * A2 - available for use
47 addi a2, a1, (___xtensa_irq_bsa_t_hifi_OFFSET + XCHAL_CP1_SA_ALIGN - 1)
49 and a2, a2, a3
51 xchal_cp1_store a2 a3 a3 a3 a3 /* Only A2 and A3 are used by macro */
Dxtensa_asm2_util.S32 * Call with CALL0, with A2/A3 available as scratch. Pushes the high
41 /* Generate a rotated (modulo NREGS/4 bits!) WINDOWSTART in A2
45 rsr a2, WINDOWSTART
46 slli a3, a2, (XCHAL_NUM_AREGS / 4)
47 or a2, a2, a3
50 srl a2, a2
60 bbsi a2, 1, _high_gpr_spill_done
67 bbsi a2, 2, _high_gpr_spill_done
74 bbsi a2, 3, _high_gpr_spill_done
97 * CALL0, leaving A2/A3 available as scratch.
[all …]
Dwindow_vectors.S33 * Registers a2 and up may contain return values.
58 s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */
80 l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */
102 rsr a2, PS
103 extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
107 xor a2, a2, a3 /* flip changed bits in old window base */
108 wsr a2, PS /* update PS.OWB to new window base */
137 s32e a2, a9, -8 /* save a2 to call[j+1]'s stack frame */
164 l32e a2, a9, -8 /* restore a2 from call[i+1]'s stack frame */
195 s32e a2, a13, -8 /* save a2 to call[j+1]'s stack frame */
[all …]
Ddebug_helpers_asm.S23 /* a2, a3, a4 should be out arguments for i PC, i SP, i-1 PC respectively.
30 /* Store value of i PC in a2 */
31 s32i a7, a2, 0
/Zephyr-latest/include/zephyr/arch/xtensa/
Dsyscall.h57 * a2 a6, a3, a4, a5, a8, a9
70 register uintptr_t a2 __asm__("%a2") = call_id; in arch_syscall_invoke6()
79 : "=r" (a2) in arch_syscall_invoke6()
80 : "r" (a2), "r" (a6), "r" (a3), "r" (a4), in arch_syscall_invoke6()
84 return a2; in arch_syscall_invoke6()
95 register uintptr_t a2 __asm__("%a2") = call_id; in arch_syscall_invoke5()
103 : "=r" (a2) in arch_syscall_invoke5()
104 : "r" (a2), "r" (a6), "r" (a3), "r" (a4), in arch_syscall_invoke5()
108 return a2; in arch_syscall_invoke5()
119 register uintptr_t a2 __asm__("%a2") = call_id; in arch_syscall_invoke4()
[all …]
/Zephyr-latest/include/zephyr/arch/riscv/
Dsyscall.h46 register unsigned long a2 __asm__ ("a2") = arg3; in arch_syscall_invoke6()
54 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), in arch_syscall_invoke6()
67 register unsigned long a2 __asm__ ("a2") = arg3; in arch_syscall_invoke5()
74 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (t0) in arch_syscall_invoke5()
85 register unsigned long a2 __asm__ ("a2") = arg3; in arch_syscall_invoke4()
91 : "r" (a1), "r" (a2), "r" (a3), "r" (t0) in arch_syscall_invoke4()
102 register unsigned long a2 __asm__ ("a2") = arg3; in arch_syscall_invoke3()
107 : "r" (a1), "r" (a2), "r" (t0) in arch_syscall_invoke3()
/Zephyr-latest/tests/drivers/tee/optee/src/
Dmain.c32 typedef void (*smc_cb_t)(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3,
42 uint32_t a2; member
54 void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3, in arm_smccc_smc() argument
61 res->a2 = OPTEE_MSG_UID_2; in arm_smccc_smc()
75 t_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
78 wait_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
81 send_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
86 void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3, in arm_smccc_hvc() argument
114 void fast_call(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3, in fast_call() argument
120 t_call.a2 = a2; in fast_call()
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/Zephyr-latest/arch/xtensa/core/startup/
Dreset_vector.S105 movi a2, XDM_MISC_PWRSTAT
111 rer a7, a2
202 rsr a2, ICOUNTLEVEL
206 bltui a2, 12, 1f
272 movi a2, _ResetSync /* address of sync variable */
276 beqz a2, .Ldonesync /* skip if no sync variable */
278 s32i a0, a2, 0 /* clear sync variable */
285 movi a2, XER_MPSCORE
286 wer a0, a2
296 movi a2, _memmap_vecbase_reset
[all …]
/Zephyr-latest/drivers/console/
Dxtensa_sim_console.c22 register int a2 __asm__ ("a2") = SYS_write; in arch_printk_char_out()
26 register int ret_val __asm__ ("a2"); in arch_printk_char_out()
32 : "a" (a2), "a" (a3), "a" (a4), "a" (a5) in arch_printk_char_out()
Dwinstream_console.c29 register int a2 __asm__("a2") = 4; /* SYS_write */ in winstream_console_trace_out()
34 __asm__ volatile("simcall" : "+r"(a2), "+r"(a3) : "r"(a4), "r"(a5) : "memory"); in winstream_console_trace_out()
/Zephyr-latest/subsys/logging/backends/
Dlog_backend_xtensa_sim.c25 register int a2 __asm__ ("a2") = SYS_write; in char_out()
31 : "=a"(a2), "=a"(a3) in char_out()
32 : "a"(a2), "a"(a3), "a"(a4), "a"(a5)); in char_out()
/Zephyr-latest/include/zephyr/arch/arm64/
Darm-smccc.h17 unsigned long a2; member
41 unsigned long a2, unsigned long a3,
54 unsigned long a2, unsigned long a3,
/Zephyr-latest/tests/bluetooth/controller/ctrl_sw_privacy_unit/src/
Dmain.c48 bt_addr_t a1, a2, a3, a4, a5; in helper_prpa_add() local
52 bt_addr_copy(&a2, BT_ADDR_INIT(0x22, 0x23, 0x24, 0x25, 0x26, 0x27)); in helper_prpa_add()
62 prpa_cache_add(&a2); in helper_prpa_add()
63 pos = prpa_cache_find(&a2); in helper_prpa_add()
91 bt_addr_t a1, a2, a3, a4, a5; in helper_trpa_add() local
95 bt_addr_copy(&a2, BT_ADDR_INIT(0x22, 0x23, 0x24, 0x25, 0x26, 0x27)); in helper_trpa_add()
105 trpa_cache_add(&a2, 1); in helper_trpa_add()
106 pos = trpa_cache_find(&a2, 1); in helper_trpa_add()
/Zephyr-latest/arch/xtensa/include/
Dxtensa_asm2_s.h160 * have been modified but A2/A3 have not, and the shift/loop
344 * interrupted/old stack) in A1, a handler function in A2, and a "new"
350 * A2 has the return value of the called function, and A3 is
356 mov a6, a3 /* place "new sp" in the next frame's A2 */
357 mov a10, a1 /* pass "context handle" in 2nd frame's A2 */
359 mov a11, a2 /* handler in 2nd frame's A3, next frame's A7 */
368 mov a2, a6 /* copy return value */
377 mov a1, a2
378 rsr.ZSR_EPS a2
379 wsr.ps a2
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/Zephyr-latest/drivers/sip_svc/
Dsip_smc_intel_socfpga.c97 if ((void *)request->a2 != NULL) { in intel_sip_smc_plat_update_trans_id()
98 data = (uint32_t *)request->a2; in intel_sip_smc_plat_update_trans_id()
112 if (request->a2) { in intel_sip_smc_plat_free_async_memory()
113 k_free((void *)request->a2); in intel_sip_smc_plat_free_async_memory()
118 unsigned long *a1, unsigned long *a2, unsigned long *a3, in intel_sip_smc_plat_async_res_req() argument
127 *a2 = (unsigned long)buf; in intel_sip_smc_plat_async_res_req()
197 LOG_DBG("\tres->a2 %08lx", res->a2); in intel_sip_secure_monitor_call()
/Zephyr-latest/drivers/tee/optee/
Doptee_smc.h128 * described above. May optionally return a 32-bit build identifier in a2,
155 * a2 Lower 32 bits of a 64-bit physical pointer to a struct optee_msg_arg
164 * a2 Lower 32 bits of a 64-bit shared memory cookie
220 * a2 Size of of SHM
246 * a2 if a1 == OPTEE_SMC_L2CC_MUTEX_SET_ADDR, upper 32bit of a 64bit
256 * a2 if a1 == OPTEE_SMC_L2CC_MUTEX_GET_ADDR, upper 32bit of a 64bit
282 * a2-6 Not used
288 * a2 The maximum secure world notification number
298 * a2-7 Preserved
341 * a2 Lower 32 bits of a 64-bit Shared memory cookie
[all …]
/Zephyr-latest/include/zephyr/bluetooth/
Dcs.h135 * | 0 | A1 A2 |
136 * | 1 | A2 A1 |
144 * | 0 | A1 A2 A3 |
145 * | 1 | A2 A1 A3 |
146 * | 2 | A1 A3 A2 |
147 * | 3 | A3 A1 A2 |
148 * | 4 | A3 A2 A1 |
149 * | 5 | A2 A3 A1 |
157 * | 0 | A1 A2 A3 A4 |
158 * | 1 | A2 A1 A3 A4 |
[all …]
/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dpower.c122 " movi a2, 0x40020\n\t"/* PS_UM|PS_WOE */
123 " wsr a2, PS\n\t"
128 " rsr a2, PRID\n\t"
130 " mull a2, a2, a3\n\t"
131 " add a2, a2, a3\n\t"
132 " add a1, a1, a2\n\t"
194 __asm__ volatile ("rsil a2, 0"); in pm_state_exit_post_ops()
/Zephyr-latest/tests/lib/cmsis_dsp/common/
Dtest_common.h35 #define DEFINE_TEST_VARIANT2(suite, name, variant, a1, a2) \ argument
38 test_##name(a1, a2); \
41 #define DEFINE_TEST_VARIANT3(suite, name, variant, a1, a2, a3) \ argument
44 test_##name(a1, a2, a3); \
47 #define DEFINE_TEST_VARIANT4(suite, name, variant, a1, a2, a3, a4) \ argument
50 test_##name(a1, a2, a3, a4); \
53 #define DEFINE_TEST_VARIANT5(suite, name, variant, a1, a2, a3, a4, a5) \ argument
56 test_##name(a1, a2, a3, a4, a5); \
59 #define DEFINE_TEST_VARIANT6(suite, name, variant, a1, a2, a3, a4, a5, a6) \ argument
62 test_##name(a1, a2, a3, a4, a5, a6); \
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/Zephyr-latest/subsys/bluetooth/crypto/
Dbt_crypto.c57 const bt_addr_le_t *a2, uint8_t *mackey, uint8_t *ltk) in bt_crypto_f5() argument
68 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* a2 */ in bt_crypto_f5()
90 m[44] = a2->type; in bt_crypto_f5()
91 sys_memcpy_swap(m + 45, a2->a.val, 6); in bt_crypto_f5()
118 const uint8_t *iocap, const bt_addr_le_t *a1, const bt_addr_le_t *a2, in bt_crypto_f6() argument
131 LOG_DBG("a2 %s", bt_hex(a2, 7)); in bt_crypto_f6()
142 m[58] = a2->type; in bt_crypto_f6()
143 memcpy(m + 59, a2->a.val, 6); in bt_crypto_f6()
144 sys_memcpy_swap(m + 59, a2->a.val, 6); in bt_crypto_f6()
/Zephyr-latest/arch/riscv/core/
Dcoredump.c27 uint64_t a2; member
48 uint32_t a2;
97 arch_blk.r.a2 = esf->a2; in arch_coredump_info_dump()
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dpower.c232 " movi a2, " STRINGIFY(PS_UM | PS_WOE | PS_INTLEVEL(XCHAL_EXCM_LEVEL)) "\n\t"
233 " wsr a2, PS\n\t"
238 " rsr a2, PRID\n\t"
240 " mull a2, a2, a3\n\t"
241 " add a2, a2, a3\n\t"
242 " add a1, a1, a2\n\t"
251 " movi a2, " STRINGIFY(PS_UM | PS_WOE | PS_INTLEVEL(XCHAL_EXCM_LEVEL)) "\n\t" in power_off_exit()
252 " wsr a2, PS\n\t" in power_off_exit()
429 __asm__ volatile ("rsil a2, 0"); in pm_state_exit_post_ops()

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