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/Zephyr-Core-3.4.0/arch/xtensa/core/
Dxtensa-asm2-util.S32 * Call with CALL0, with A2/A3 available as scratch. Pushes the high
41 /* Generate a rotated (modulo NREGS/4 bits!) WINDOWSTART in A2
45 rsr a2, WINDOWSTART
46 slli a3, a2, (XCHAL_NUM_AREGS / 4)
47 or a2, a2, a3
50 srl a2, a2
60 bbsi a2, 1, _high_gpr_spill_done
67 bbsi a2, 2, _high_gpr_spill_done
74 bbsi a2, 3, _high_gpr_spill_done
97 * CALL0, leaving A2/A3 available as scratch.
[all …]
Dwindow_vectors.S33 * Registers a2 and up may contain return values.
58 s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */
80 l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */
102 rsr a2, PS
103 extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
107 xor a2, a2, a3 /* flip changed bits in old window base */
108 wsr a2, PS /* update PS.OWB to new window base */
137 s32e a2, a9, -8 /* save a2 to call[j+1]'s stack frame */
164 l32e a2, a9, -8 /* restore a2 from call[i+1]'s stack frame */
195 s32e a2, a13, -8 /* save a2 to call[j+1]'s stack frame */
[all …]
Ddebug_helpers_asm.S23 /* a2, a3, a4 should be out arguments for i PC, i SP, i-1 PC respectively.
30 /* Store value of i PC in a2 */
31 s32i a7, a2, 0
/Zephyr-Core-3.4.0/include/zephyr/arch/riscv/
Dsyscall.h46 register unsigned long a2 __asm__ ("a2") = arg3; in arch_syscall_invoke6()
54 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), in arch_syscall_invoke6()
67 register unsigned long a2 __asm__ ("a2") = arg3; in arch_syscall_invoke5()
74 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (t0) in arch_syscall_invoke5()
85 register unsigned long a2 __asm__ ("a2") = arg3; in arch_syscall_invoke4()
91 : "r" (a1), "r" (a2), "r" (a3), "r" (t0) in arch_syscall_invoke4()
102 register unsigned long a2 __asm__ ("a2") = arg3; in arch_syscall_invoke3()
107 : "r" (a1), "r" (a2), "r" (t0) in arch_syscall_invoke3()
/Zephyr-Core-3.4.0/arch/xtensa/core/startup/
Dreset-vector.S105 movi a2, XDM_MISC_PWRSTAT
111 rer a7, a2
202 rsr a2, ICOUNTLEVEL
206 bltui a2, 12, 1f
272 movi a2, _ResetSync /* address of sync variable */
276 beqz a2, .Ldonesync /* skip if no sync variable */
278 s32i a0, a2, 0 /* clear sync variable */
285 movi a2, XER_MPSCORE
286 wer a0, a2
296 movi a2, _memmap_vecbase_reset
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/Zephyr-Core-3.4.0/tests/lib/cmsis_dsp/common/
Dtest_common.h36 #define DEFINE_TEST_VARIANT2(suite, name, variant, a1, a2) \ argument
39 test_##name(a1, a2); \
42 #define DEFINE_TEST_VARIANT3(suite, name, variant, a1, a2, a3) \ argument
45 test_##name(a1, a2, a3); \
48 #define DEFINE_TEST_VARIANT4(suite, name, variant, a1, a2, a3, a4) \ argument
51 test_##name(a1, a2, a3, a4); \
54 #define DEFINE_TEST_VARIANT5(suite, name, variant, a1, a2, a3, a4, a5) \ argument
57 test_##name(a1, a2, a3, a4, a5); \
60 #define DEFINE_TEST_VARIANT6(suite, name, variant, a1, a2, a3, a4, a5, a6) \ argument
63 test_##name(a1, a2, a3, a4, a5, a6); \
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/Zephyr-Core-3.4.0/arch/xtensa/include/
Dxtensa-asm2-s.h156 * have been modified but A2/A3 have not, and the shift/loop
338 * interrupted/old stack) in A1, a handler function in A2, and a "new"
344 * A2 has the return value of the called function, and A3 is
350 mov a6, a3 /* place "new sp" in the next frame's A2 */
351 mov a10, a1 /* pass "context handle" in 2nd frame's A2 */
353 mov a11, a2 /* handler in 2nd frame's A3, next frame's A7 */
362 mov a2, a6 /* copy return value */
371 mov a1, a2
372 rsr.ZSR_EPS a2
373 wsr.PS a2
[all …]
/Zephyr-Core-3.4.0/drivers/console/
Dxtensa_sim_console.c20 register int a2 __asm__ ("a2") = SYS_write; in console_out()
24 register int ret_val __asm__ ("a2"); in console_out()
30 : "a" (a2), "a" (a3), "a" (a4), "a" (a5) in console_out()
Dwinstream_console.c27 register int a2 __asm__("a2") = 4; /* SYS_write */ in winstream_console_trace_out()
32 __asm__ volatile("simcall" : "+r"(a2), "+r"(a3) : "r"(a4), "r"(a5) : "memory"); in winstream_console_trace_out()
/Zephyr-Core-3.4.0/subsys/logging/backends/
Dlog_backend_xtensa_sim.c25 register int a2 __asm__ ("a2") = SYS_write; in char_out()
31 : "=a"(a2), "=a"(a3) in char_out()
32 : "a"(a2), "a"(a3), "a"(a4), "a"(a5)); in char_out()
/Zephyr-Core-3.4.0/include/zephyr/arch/arm64/
Darm-smccc.h17 unsigned long a2; member
41 unsigned long a2, unsigned long a3,
54 unsigned long a2, unsigned long a3,
/Zephyr-Core-3.4.0/drivers/sip_svc/
Dsip_smc_intel_socfpga.c96 if ((void *)request->a2 != NULL) { in intel_sip_smc_plat_update_trans_id()
97 data = (uint32_t *)request->a2; in intel_sip_smc_plat_update_trans_id()
111 if (request->a2) { in intel_sip_smc_plat_free_async_memory()
112 k_free((void *)request->a2); in intel_sip_smc_plat_free_async_memory()
117 unsigned long *a1, unsigned long *a2, unsigned long *a3, in intel_sip_smc_plat_async_res_req() argument
126 *a2 = (unsigned long)buf; in intel_sip_smc_plat_async_res_req()
190 LOG_DBG("\tres->a2 %08lx", res->a2); in intel_sip_secure_monitor_call()
/Zephyr-Core-3.4.0/subsys/bluetooth/crypto/
Dbt_crypto.c79 const bt_addr_le_t *a2, uint8_t *mackey, uint8_t *ltk) in bt_crypto_f5() argument
90 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* a2 */ in bt_crypto_f5()
112 m[44] = a2->type; in bt_crypto_f5()
113 sys_memcpy_swap(m + 45, a2->a.val, 6); in bt_crypto_f5()
140 const uint8_t *iocap, const bt_addr_le_t *a1, const bt_addr_le_t *a2, in bt_crypto_f6() argument
153 LOG_DBG("a2 %s", bt_hex(a2, 7)); in bt_crypto_f6()
164 m[58] = a2->type; in bt_crypto_f6()
165 memcpy(m + 59, a2->a.val, 6); in bt_crypto_f6()
166 sys_memcpy_swap(m + 59, a2->a.val, 6); in bt_crypto_f6()
Dbt_crypto.h53 * @param[in] a2 56-bit
61 const bt_addr_le_t *a2, uint8_t *mackey, uint8_t *ltk);
74 * @param[in] a2 56-bit
81 const uint8_t *iocap, const bt_addr_le_t *a1, const bt_addr_le_t *a2,
/Zephyr-Core-3.4.0/soc/xtensa/intel_adsp/ace/
Dpower.c172 " movi a2, 0x40020\n\t"/* PS_UM|PS_WOE */
173 " wsr a2, PS\n\t"
178 " rsr a2, PRID\n\t"
180 " mull a2, a2, a3\n\t"
181 " add a2, a2, a3\n\t"
182 " add a1, a1, a2\n\t"
191 " movi a2, 0x40020\n\t"/* PS_UM|PS_WOE */ in power_off_exit()
192 " wsr a2, PS\n\t" in power_off_exit()
/Zephyr-Core-3.4.0/tests/bluetooth/ctrl_sw_privacy_unit/src/
Dmain.c42 bt_addr_t a1, a2, a3, a4, a5; in helper_privacy_add() local
46 bt_addr_copy(&a2, BT_ADDR_INIT(0x22, 0x23, 0x24, 0x25, 0x26, 0x27)); in helper_privacy_add()
56 prpa_cache_add(&a2); in helper_privacy_add()
57 pos = prpa_cache_find(&a2); in helper_privacy_add()
/Zephyr-Core-3.4.0/arch/riscv/core/
Dcoredump.c21 uint32_t a2; member
69 arch_blk.r.a2 = esf->a2; in arch_coredump_info_dump()
Duserspace.S29 sw a5, 0(a2) # Init error value to 0
50 sw a4, 0(a2)
Dpmp.S20 * bool clear_trailing_entries, // a2
89 beqz a2, done
/Zephyr-Core-3.4.0/soc/xtensa/intel_adsp/common/
Dmultiprocessing.c80 " rsr a2, PRID \n\t"
81 " sub a2, a2, a1 \n\t"
82 " bnez a2, soc_mp_idle \n\t"
/Zephyr-Core-3.4.0/samples/arch/mpu/mpu_test/
DREADME.rst55 <err> os: r0/a1: 0x00009a5c r1/a2: 0x00000008 r2/a3: 0x20001aa8
71 <err> os: r0/a1: 0x00000000 r1/a2: 0x0000000e r2/a3: 0x0badc0de
85 <err> os: r0/a1: 0x00009a5c r1/a2: 0x00000001 r2/a3: 0x20001aa8
113 <err> os: r0/a1: 0x0800a54c r1/a2: 0x00000008 r2/a3: 0x08003
126 <err> os: r0/a1: 0x00000000 r1/a2: 0x0000000e r2/a3: 0x0000e
/Zephyr-Core-3.4.0/tests/arch/arm/arm_interrupt/
DREADME.txt61 E: r0/a1: 0x20000000 r1/a2: 0x00000000 r2/a3: 0x20001e40
75 E: r0/a1: 0x00000003 r1/a2: 0x200020b8 r2/a3: 0x00000003
84 E: r0/a1: 0x00000004 r1/a2: 0x200020b8 r2/a3: 0x00000004
96 E: r0/a1: 0x00000004 r1/a2: 0x000000cf r2/a3: 0x00000000
108 E: r0/a1: 0x00000004 r1/a2: 0x00000017 r2/a3: 0x00000000
119 E: r0/a1: 0xdde8d9e7 r1/a2: 0x5510538d r2/a3: 0x00000d74
132 E: r0/a1: 0x00000000 r1/a2: 0x00000001 r2/a3: 0x00000002
/Zephyr-Core-3.4.0/scripts/tests/twister/test_data/quarantines/
Dwith_regexp.yaml5 comment: "a2 and c2 on x86"
/Zephyr-Core-3.4.0/include/zephyr/drivers/sip_svc/
Dsip_svc_driver.h72 unsigned long *a1, unsigned long *a2, unsigned long *a3,
259 * @param a2 Argument 2 for supervisory call.
271 unsigned long *a1, unsigned long *a2, unsigned long *a3,
275 unsigned long *a1, unsigned long *a2, in z_impl_sip_svc_plat_async_res_req() argument
287 __ASSERT(a2, "a2 shouldn't be NULL"); in z_impl_sip_svc_plat_async_res_req()
295 return api->sip_svc_plat_async_res_req(dev, a0, a1, a2, a3, a4, a5, a6, a7, buf, size); in z_impl_sip_svc_plat_async_res_req()
/Zephyr-Core-3.4.0/tests/net/conn_mgr_conn/src/
Dtest_ifaces.c31 /* Create three ifaces, a1, a2, b such that:
32 * iface a1 and a2 share L2 connectivity implementation a

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