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/Zephyr-latest/dts/bindings/w1/
Dmaxim,ds2482-800.yaml4 description: DS4282-800, 8-Channel 1-Wire Master
6 compatible: "maxim,ds2482-800"
10 bus: ds2482-800
Dmaxim,ds2482-800-channel.yaml4 description: DS4282-800, 8-Channel 1-Wire Master (Channel driver)
6 compatible: "maxim,ds2482-800-channel"
10 on-bus: ds2482-800
/Zephyr-latest/drivers/modem/
DKconfig.hl7800147 bool "Band 18 (800MHz)"
149 Enable Band 18 (800MHz)
152 bool "Band 19 (800MHz)"
154 Enable Band 19 (800MHz)
157 bool "Band 20 (800MHz)"
160 Enable Band 20 (800MHz)
168 bool "Band 26 (800MHz)"
170 Enable Band 26 (800MHz)
173 bool "Band 27 (800MHz)"
175 Enable Band 27 (800MHz)
/Zephyr-latest/samples/drivers/w1/scanner/
Dds2482-800.overlay5 compatible = "maxim,ds2482-800";
12 compatible = "maxim,ds2482-800-channel";
Dsample.yaml8 sample.drivers.w1.scanner.ds2482-800:
10 extra_args: DTC_OVERLAY_FILE=ds2482-800.overlay
/Zephyr-latest/soc/nxp/imx/imx8m/m7/
Dsoc.c64 .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
88 * to 800Mhz when power up the SOC, meanwhile A core would enable SYSTEM PLL1, SYSTEM PLL2 in SOC_ClockInit()
99 /* Set root clock to 800M */ in SOC_ClockInit()
138 /* Set ECSPI1 source to SYSTEM PLL1 800MHZ */ in SOC_ClockInit()
140 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()
145 /* Set ECSPI2 source to SYSTEM PLL1 800MHZ */ in SOC_ClockInit()
147 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()
152 /* Set ECSPI3 source to SYSTEM PLL1 800MHZ */ in SOC_ClockInit()
154 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()
/Zephyr-latest/tests/drivers/w1/w1_api/
Dds2482-800.overlay9 compatible = "maxim,ds2482-800";
16 compatible = "maxim,ds2482-800-channel";
Dtestcase.yaml19 drivers.w1.ds2482-800:
21 extra_args: DTC_OVERLAY_FILE=ds2482-800.overlay
/Zephyr-latest/drivers/clock_control/
Dclock_control_r8a7795_cpg_mssr.c46 RCAR_CORE_CLK_INFO_ITEM(R8A7795_CLK_SD0H, 0x0074, RCAR_CPG_NONE, RCAR_CPG_MHZ(800)),
47 RCAR_CORE_CLK_INFO_ITEM(R8A7795_CLK_SD0, 0x0074, R8A7795_CLK_SD0H, RCAR_CPG_MHZ(800)),
49 RCAR_CORE_CLK_INFO_ITEM(R8A7795_CLK_SD1H, 0x0078, RCAR_CPG_NONE, RCAR_CPG_MHZ(800)),
50 RCAR_CORE_CLK_INFO_ITEM(R8A7795_CLK_SD1, 0x0078, R8A7795_CLK_SD1H, RCAR_CPG_MHZ(800)),
52 RCAR_CORE_CLK_INFO_ITEM(R8A7795_CLK_SD2H, 0x0268, RCAR_CPG_NONE, RCAR_CPG_MHZ(800)),
53 RCAR_CORE_CLK_INFO_ITEM(R8A7795_CLK_SD2, 0x0268, R8A7795_CLK_SD2H, RCAR_CPG_MHZ(800)),
55 RCAR_CORE_CLK_INFO_ITEM(R8A7795_CLK_SD3H, 0x026C, RCAR_CPG_NONE, RCAR_CPG_MHZ(800)),
56 RCAR_CORE_CLK_INFO_ITEM(R8A7795_CLK_SD3, 0x026C, R8A7795_CLK_SD3H, RCAR_CPG_MHZ(800)),
58 RCAR_CORE_CLK_INFO_ITEM(R8A7795_CLK_CANFD, 0x0244, RCAR_CPG_NONE, RCAR_CPG_MHZ(800)),
/Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/
Dsoc.c101 /* Set root clock to 800MHZ/ 2= 400MHZ */ in SOC_ClockInit()
135 /* Set ECSPI1 source to SYSTEM PLL1 800MHZ */ in SOC_ClockInit()
137 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()
142 /* Set ECSPI2 source to SYSTEM PLL1 800MHZ */ in SOC_ClockInit()
144 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()
149 /* Set ECSPI3 source to SYSTEM PLL1 800MHZ */ in SOC_ClockInit()
151 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()
/Zephyr-latest/drivers/w1/
DCMakeLists.txt12 zephyr_library_sources_ifdef(CONFIG_W1_DS2482_800 w1_ds2482-800.c w1_ds2482-800_channel.c)
DKconfig.ds2482-8005 bool "DS2482-800, 8-Channel 1-Wire Master"
Dw1_ds2482_84_common.h18 #define CMD_CHSL 0xc3 /* DS2482-800 only */
28 #define REG_CHANNEL 0xd2 /* DS2482-800 only */
64 * Channel Selection Codes, DS2482-800 only
76 * Channel Selection Codes (read back values), DS2482-800 only
/Zephyr-latest/tests/drivers/build_all/w1/
Dapp.overlay52 test_i2c_ds2482_800: ds2482-800@0 {
53 compatible = "maxim,ds2482-800";
60 compatible = "maxim,ds2482-800-channel";
/Zephyr-latest/tests/crypto/tinycrypt/src/
Dcbc_mode.c36 * - AES128 CBC mode encryption SP 800-38a tests
49 * NIST test vectors from SP 800-38a:
102 * NIST SP 800-38a CBC Test for encryption and decryption.
121 TC_PRINT("CBC test #1 (encryption SP 800-38a tests):\n"); in ZTEST()
127 "CBC test #1 (encryption SP 800-38a tests) failed"); in ZTEST()
133 TC_PRINT("CBC test #2 (decryption SP 800-38a tests):\n"); in ZTEST()
142 &a), "CBC test #2 (decryption SP 800-38a tests) failed"); in ZTEST()
Dctr_mode.c37 * - AES128 CTR mode encryption SP 800-38a tests
50 * NIST SP 800-38a CTR Test for encryption and decryption.
100 TC_PRINT("CTR test #1 (encryption SP 800-38a tests):\n"); in test_ctr_sp_800_38a_encrypt_decrypt()
109 "CTR test #1 (encryption SP 800-38a tests) failed"); in test_ctr_sp_800_38a_encrypt_decrypt()
113 TC_PRINT("CTR test #2 (decryption SP 800-38a tests):\n"); in test_ctr_sp_800_38a_encrypt_decrypt()
120 "CTR test #2 (decryption SP 800-38a tests) failed"); in test_ctr_sp_800_38a_encrypt_decrypt()
Dcmac_mode.c1 /* test_cmac_mode.c - TinyCrypt AES-CMAC tests (including SP 800-38B tests) */
34 * This module tests the following AES-CMAC test (including SP 800-38B):
38 * - CMAC test #2 null msg (SP 800-38B test vector #1)
39 * - CMAC test #3 1 block msg (SP 800-38B test vector #2)
40 * - CMAC test #4 320 bit msg (SP 800-38B test vector #3)
41 * - CMAC test #5 512 bit msg(SP 800-38B test vector #4)
121 TC_PRINT("Performing CMAC test #2 (SP 800-38B test vector #1):\n"); in verify_cmac_null_msg()
147 TC_PRINT("Performing CMAC test #3 (SP 800-38B test vector #2):\n"); in verify_cmac_1_block_msg()
178 TC_PRINT("Performing CMAC test #4 (SP 800-38B test vector #3):\n"); in verify_cmac_320_bit_msg()
212 TC_PRINT("Performing CMAC test #5 (SP 800-38B test vector #4)\n"); in verify_cmac_512_bit_msg()
/Zephyr-latest/dts/bindings/sensor/
Dinvensense,icm42670.yaml24 Power-on reset value is 800.
28 - 800
45 Power-on reset value is 800.
49 - 800
Dadi,adxl372-common.yaml13 1 # 800Hz
31 2 # 800Hz
Dnxp,fxos8700-common.yaml97 ODR=800 Hz and pls_hpf_en=0, the resolution is 0.625 ms/LSB.
107 configuration (HP_FILTER_CUTOFF[pls_hpf_en]). For ODR=800 Hz and
123 For ODR=800 Hz and pls_hpf_en=0, the resolution is 1.25 ms/LSB.
/Zephyr-latest/dts/bindings/led_strip/
Dworldsemi,ws2812-rpi_pico-pio.yaml39 For example, T0=3, T1=3, T2=4 and the frequency is 800kHz case,
41 (1 / 800kHz) * (3/10) = 375ns
43 (1 / 800kHz) * ((4+3)/10) = 875ns
/Zephyr-latest/boards/shields/st_b_lcd40_dsi1_mb1166/
Dst_b_lcd40_dsi1_mb1166.overlay27 height = <800>;
39 width = <800>;
Dst_b_lcd40_dsi1_mb1166_a09.overlay27 height = <800>;
39 width = <800>;
/Zephyr-latest/samples/drivers/video/capture_to_lvgl/
DREADME.rst53 [00:00:02.780,000] <inf> main: RGBP width [800; 800; 0] height [600; 600; 0]
63 [00:00:02.780,000] <inf> main: JPEG width [800; 800; 0] height [600; 600; 0]
/Zephyr-latest/drivers/sensor/bosch/bmi160/
DKconfig138 bool "800 Hz"
209 bool "800 Hz"

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