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/Zephyr-latest/soc/nxp/imx/imx8m/m4_quad/
Dsoc.c71 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
73 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
77 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
79 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
83 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
85 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
89 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
91 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
/Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/
Dsoc.c108 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
110 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
114 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
116 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
120 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
122 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
126 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
128 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
137 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()
144 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()
[all …]
/Zephyr-latest/soc/nxp/imx/imx8m/m7/
Dsoc.c111 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
113 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
117 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
119 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
123 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
125 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
129 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
131 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
140 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()
147 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dvishay,vcnl4040.yaml43 - 80
75 default: 80
76 # default of 80 is POR (0b00) for ALS_CONF[ALS_IT] register
79 - 80
/Zephyr-latest/tests/boards/intel_adsp/cache/src/
Dmain.c33 *uncached = 80; in ZTEST()
36 zassert_equal(*cached, 80, NULL); in ZTEST()
37 zassert_equal(*uncached, 80, NULL); in ZTEST()
43 zassert_equal(*uncached, 80, NULL); in ZTEST()
/Zephyr-latest/samples/net/sockets/websocket_client/
Doverlay-tls.conf2 CONFIG_NET_BUF_RX_COUNT=80
3 CONFIG_NET_BUF_TX_COUNT=80
/Zephyr-latest/samples/net/sockets/http_client/
Doverlay-tls.conf2 CONFIG_NET_BUF_RX_COUNT=80
3 CONFIG_NET_BUF_TX_COUNT=80
/Zephyr-latest/samples/net/sockets/echo_server/
Doverlay-tls.conf2 CONFIG_NET_BUF_RX_COUNT=80
3 CONFIG_NET_BUF_TX_COUNT=80
/Zephyr-latest/tests/subsys/logging/log_immediate/
Dtestcase.yaml10 timeout: 80
21 timeout: 80
/Zephyr-latest/boards/shields/waveshare_epaper/
Dwaveshare_epaper_gdeh0213b72.overlay38 80 60 40 00 00 00 00
40 80 60 40 00 00 00 00
62 80 00 00 00 00 00 00
64 80 00 00 00 00 00 00
/Zephyr-latest/drivers/watchdog/
DKconfig.cc32xx19 80 Mhz: 0xFFFFFFFF / (80e9 / 1000)
/Zephyr-latest/soc/espressif/common/
DKconfig.esptool102 bool "80 MHz"
119 This is an invisible item, used to define the targets that defaults to use 80MHz Flash SPI speed.
123 # On some of the ESP chips, max boot frequency would be equal to (or even lower than) 80m.
124 # We currently define this to `80m`.
125 default '80m' if ESPTOOLPY_FLASHFREQ_120M
126 default '80m' if ESPTOOLPY_FLASHFREQ_80M
/Zephyr-latest/tests/drivers/input/gpio_kbd_matrix/boards/
Dnative_sim.overlay18 debounce-down-ms = <80>;
30 debounce-up-ms = <80>;
43 debounce-down-ms = <80>;
/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc55S06_ns.dtsi33 * Combine SRAM0, SRAM1, SRAM2 for total of 80K RAM
37 reg = <0x20000000 DT_SIZE_K(80)>;
/Zephyr-latest/samples/net/sockets/echo_client/
Dprj.conf29 CONFIG_NET_BUF_RX_COUNT=80
30 CONFIG_NET_BUF_TX_COUNT=80
/Zephyr-latest/tests/bsim/net/sockets/echo_test/
Dprj.conf30 CONFIG_NET_BUF_RX_COUNT=80
31 CONFIG_NET_BUF_TX_COUNT=80
/Zephyr-latest/drivers/espi/
DKconfig.it8xxx2131 # Port 80 and 81 I/O cycles share the same interrupt source and there is no
135 # It means that the Host must alwasy write 2 bytes of data to port 80 otherwise
142 This allows EC to accept 2 bytes of port 80 data written from the Host.
/Zephyr-latest/boards/native/doc/
Dcomponents_natsim.svg480&quot; as=&quot;geometry&quot; /&gt;&#xA; &lt;/mxCell&gt;&#xA; &lt;mxCell id=&quot…
/Zephyr-latest/tests/drivers/build_all/gpio/
Dtestcase.yaml46 - CONFIG_ADC_INIT_PRIORITY=80
62 - CONFIG_ADC_INIT_PRIORITY=80
/Zephyr-latest/doc/hardware/peripherals/
D1-Wire_bus_topology.drawio.svg480" height="80" fill="#ffffff" stroke="rgb(0, 0, 0)" pointer-events="none"/><g transform="translat…
/Zephyr-latest/drivers/ieee802154/
DKconfig.cc13xx_cc26xx16 default 80
74 default -80 # Based on SUN FSK, 200 kHz bit rate, no FEC, see IEEE 802.15.4-2020, section 19.6.7
87 default 80
/Zephyr-latest/include/zephyr/net/
Dieee802154_pkt.h34 #define IEEE802154_MAC_RSSI_MAX 254U /* corresponds to 80 dBm */
38 #define IEEE802154_MAC_RSSI_DBM_MAX 80 /* in dBm */
52 * the minimum and maximum values are 0 (–174 dBm) and 254 (80 dBm),
115 * 0 (–174 dBm) to 254 (80 dBm).
132 * 0 (–174 dBm) to 254 (80 dBm).
167 * not available for this packet. Values above 80 dBm will
168 * be mapped to 80 dBm, values below -174 dBm will be mapped
/Zephyr-latest/tests/net/utils/src/
Dmain.c436 .address = "192.0.2.1:80", in ZTEST()
437 .len = sizeof("192.0.2.1:80") - 1, in ZTEST()
440 .sin_port = htons(80), in ZTEST()
511 .address = "192.0.2.3:80/foobar", in ZTEST()
512 .len = sizeof("192.0.2.3:80/foobar") - 1, in ZTEST()
521 .address = "192.0.2.3:80/foobar", in ZTEST()
536 .address = "192.0.2.3:80/foobar", in ZTEST()
537 .len = sizeof("192.0.2.3:80") - 1, in ZTEST()
540 .sin_port = htons(80), in ZTEST()
556 .address = "192.0.2.3:80:80", in ZTEST()
[all …]
/Zephyr-latest/tests/drivers/build_all/pwm/
Dprj.conf2 CONFIG_MFD_INIT_PRIORITY=80
/Zephyr-latest/tests/kernel/mem_slab/mslab_concept/
Dtestcase.yaml4 timeout: 80

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