| /Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/reg/ |
| D | mec172x_i2c_smb.h | 4 * SPDX-License-Identifier: Apache-2.0
36 * Size 8-bit
40 #define MCHP_I2C_SMB_CTRL_ACK BIT(0)
41 #define MCHP_I2C_SMB_CTRL_STO BIT(1)
42 #define MCHP_I2C_SMB_CTRL_STA BIT(2)
43 #define MCHP_I2C_SMB_CTRL_ENI BIT(3)
45 #define MCHP_I2C_SMB_CTRL_ESO BIT(6)
46 #define MCHP_I2C_SMB_CTRL_PIN BIT(7)
47 /* Status Read-only */
49 #define MCHP_I2C_SMB_STS_NBB BIT(0)
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| D | mec172x_ecia.h | 4 * SPDX-License-Identifier: Apache-2.0
16 #define MCHP_FIRST_GIRQ_NOS 8u
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
33 #define MCHP_ECIA_ALL_BITMAP GENMASK(26, 8)
35 /* MEC172x implements 8 priority levels. ARM NVIC 0 = highest priority */
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| D | mec172x_pcr.h | 4 * SPDX-License-Identifier: Apache-2.0
53 * CLK_REQ bits are read-only. The peripheral sets its CLK_REQ if it requires
56 * SLP_EN bit = 1 instructs HW to gate off clock tree to peripheral only if
57 * peripherals PCR CLK_REQ bit is 0.
58 * RST_EN bit = 1 will reset the peripheral at any time. The RST_EN registers
67 * SLEEP_ALL bit = 1.
68 * Execute Cortex-M4 WFI sequence. DSB(), ISB(), WFI(), NOP()
69 * Cortex-M4 will assert sleep signal to PCR block.
76 * Write bit patterns to one or more of PCR RST_EN[0, 4] registers
84 #define MCHP_PCR_SLP(bitpos) BIT(bitpos)
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| D | mec172x_espi_vw.h | 4 * SPDX-License-Identifier: Apache-2.0
13 /* Master to Slave VW register: 96-bit (3 32 bit registers) */
14 /* 32-bit word 0 (bits[31:0]) */
18 #define ESPI_M2SW0_MTOS_SRC_POS 8u
28 /* 32-bit word 1 (bits[63:32]) */
33 #define ESPI_M2SW1_SRC1_SEL_POS 8
40 #define ESPI_M2SW1_SRC_SEL_POS(n) ((n) * 8u)
41 #define ESPI_M2SW1_SRC_SEL_MASK(n) SHLU32(0xfu, ((n) * 8u))
42 #define ESPI_M2SW1_SRC_SEL_VAL(n, v) SHLU32(((v) & 0xfu), ((n) * 8u))
43 /* 32-bit word 2 (bits[95:64]) */
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| D | mec172x_p80bd.h | 4 * SPDX-License-Identifier: Apache-2.0
15 /* HDATA - Write-Only 32-bit */
20 * EC-only Data/Attributes 16-bit
22 * b[15:8] = data attributes
27 #define MCHP_P80BD_ECDA_APOS 8
30 #define MCHP_P80BD_ECDA_LANE_POS 8
42 #define MCHP_P80BD_ECDA_NE BIT(12)
43 #define MCHP_P80BD_ECDA_OVR BIT(13)
44 #define MCHP_P80BD_ECDA_THR BIT(14)
49 #define MCHP_P80BD_CFG_FLUSH_FIFO BIT(0) /* WO */
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| D | mec172x_qspi.h | 4 * SPDX-License-Identifier: Apache-2.0
38 #define MCHP_QMSPI_TX_FIFO_LEN 8u
39 #define MCHP_QMSPI_RX_FIFO_LEN 8u
49 #define MCHP_QMSPI_EXE_OFS 8u
130 #define MCHP_QMSPI_M_ACTIVATE BIT(0)
131 #define MCHP_QMSPI_M_SRST BIT(1)
132 #define MCHP_QMSPI_M_SAF_DMA_MODE_EN BIT(2)
133 #define MCHP_QMSPI_M_LDMA_RX_EN BIT(3)
134 #define MCHP_QMSPI_M_LDMA_TX_EN BIT(4)
135 #define MCHP_QMSPI_M_CPOL_POS 8u
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| D | mec172x_espi_saf.h | 4 * SPDX-License-Identifier: Apache-2.0
33 /* SAF Protection region described by 4 32-bit registers. 17 regions */
36 /* Register bit definitions */
44 #define MCHP_SAF_ECP_CMD_CTYPE_POS 8
62 #define MCHP_SAF_ECP_CMD_ERASE_32K BIT(24)
63 #define MCHP_SAF_ECP_CMD_ERASE_64K BIT(25)
82 #define MCHP_SAF_ECP_START BIT(0)
100 #define MCHP_SAF_ECP_STS_BAD_REQ_POS 8
101 #define MCHP_SAF_ECP_STS_DONE BIT(0)
102 #define MCHP_SAF_ECP_STS_DONE_TST BIT(1)
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| /Zephyr-Core-3.5.0/drivers/display/ |
| D | Kconfig.stm32_ltdc | 3 # Copyright (c) 2022 Byte-Lab d.o.o. <dev@byte-lab.com>
4 # SPDX-License-Identifier: Apache-2.0
7 bool "STM32 LCD-TFT display controller driver"
12 Enable driver for STM32 LCT-TFT display controller periheral.
19 Specify the color pixel format for the STM32 LCD-TFT display controller.
24 One pixel consists of 8-bit alpha, 8-bit red, 8-bit green and 8-bit blue value
30 One pixel consists of 8-bit red, 8-bit green and 8-bit blue value
36 One pixel consists of 5-bit red, 6-bit green and 5-bit blue value
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| /Zephyr-Core-3.5.0/drivers/can/ |
| D | can_mcp251xfd.h | 5 * SPDX-License-Identifier: Apache-2.0
18 ((flag_u32) >> ROUND_DOWN(LOG2((flag_u32)), 8))
28 #define MCP251XFD_TEF_FIFO_ITEM_SIZE 8
29 #define MCP251XFD_TX_QUEUE_ITEM_SIZE (8 + MCP251XFD_PAYLOAD_SIZE)
32 #define MCP251XFD_RX_FIFO_ITEM_SIZE (4 + 8 + MCP251XFD_PAYLOAD_SIZE)
34 #define MCP251XFD_RX_FIFO_ITEM_SIZE (8 + MCP251XFD_PAYLOAD_SIZE)
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
82 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
87 #define MCP251XFD_REG_CON_ABAT BIT(27)
98 #define MCP251XFD_REG_CON_TXQEN BIT(20)
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| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | spi_pw.h | 1 /* spi_pw.h - Penwell SPI driver definitions */
6 * SPDX-License-Identifier: Apache-2.0
41 #define PW_SPI_CTRLR0_SSE_BIT BIT(7)
42 #define PW_SPI_CTRLR0_EDSS_BIT BIT(20)
43 #define PW_SPI_CTRLR0_RIM_BIT BIT(22)
44 #define PW_SPI_CTRLR0_TIM_BIT BIT(23)
45 #define PW_SPI_CTRLR0_MOD_BIT BIT(31)
59 /* SSP Baud rate sscr0[19:8] */
66 /* [19:8] 12 bits */
67 #define PW_SPI_SCR_MASK (BIT_MASK(12) << 8)
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| D | spi_dw.h | 1 /* spi_dw.h - Designware SPI driver private definitions */
7 * SPDX-License-Identifier: Apache-2.0
25 typedef void (*spi_dw_set_bit_t)(uint8_t bit, uint32_t addr, uint32_t off);
26 typedef void (*spi_dw_clear_bit_t)(uint8_t bit, uint32_t addr, uint32_t off);
27 typedef int (*spi_dw_test_bit_t)(uint8_t bit, uint32_t addr, uint32_t off);
77 static void aux_reg_set_bit(uint8_t bit, uint32_t addr, uint32_t off) in aux_reg_set_bit() argument
79 sys_io_set_bit(addr + off/4, bit); in aux_reg_set_bit()
82 static void aux_reg_clear_bit(uint8_t bit, uint32_t addr, uint32_t off) in aux_reg_clear_bit() argument
84 sys_io_clear_bit(addr + off/4, bit); in aux_reg_clear_bit()
87 static int aux_reg_test_bit(uint8_t bit, uint32_t addr, uint32_t off) in aux_reg_test_bit() argument
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| D | spi_andes_atcspi200.h | 4 * SPDX-License-Identifier: Apache-2.0
31 #define SPI_BASE (((const struct spi_atcspi200_cfg *)(dev)->config)->base)
44 #define TFMAT_DATA_LEN_OFFSET (8)
46 #define TFMAT_CPHA_MSK BIT(0)
47 #define TFMAT_CPOL_MSK BIT(1)
48 #define TFMAT_SLVMODE_MSK BIT(2)
49 #define TFMAT_LSB_MSK BIT(3)
50 #define TFMAT_DATA_MERGE_MSK BIT(7)
51 #define TFMAT_DATA_LEN_MSK GENMASK(12, 8)
68 #define IEN_RX_FIFO_MSK BIT(2)
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| /Zephyr-Core-3.5.0/drivers/ipm/ |
| D | ipm_nrfx_ipc.h | 4 * SPDX-License-Identifier: Apache-2.0
13 * Message channels are one-way connections between cores.
19 * SIGNAL0 -> CHANNEL0 -> EVENT0
24 * EVENT1 <- CHANNEL1 <- SIGNAL1
40 IPC_EVENT_BIT(8) | \
52 [0] = BIT(0),
53 [1] = BIT(1),
54 [2] = BIT(2),
55 [3] = BIT(3),
56 [4] = BIT(4),
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| /Zephyr-Core-3.5.0/drivers/ethernet/ |
| D | eth_enc424j600_priv.h | 1 /* ENC424J600 Stand-alone Ethernet Controller with SPI
6 * SPDX-License-Identifier: Apache-2.0
136 #define ENC424J600_PSFR_PHCON1 (BIT(8) | 0x00)
137 #define ENC424J600_PSFR_PHSTAT1 (BIT(8) | 0x01)
138 #define ENC424J600_PSFR_PHANA (BIT(8) | 0x04)
139 #define ENC424J600_PSFR_PHANLPA (BIT(8) | 0x05)
140 #define ENC424J600_PSFR_PHANE (BIT(8) | 0x06)
141 #define ENC424J600_PSFR_PHCON2 (BIT(8) | 0x11)
142 #define ENC424J600_PSFR_PHSTAT2 (BIT(8) | 0x1B)
143 #define ENC424J600_PSFR_PHSTAT3 (BIT(8) | 0x1F)
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| D | eth_dwmac_priv.h | 6 * SPDX-License-Identifier: Apache-2.0
10 * DesignWare Cores Ethernet Quality-of-Service Databook
76 #define REG_READ(r) sys_read32(p->base_addr + (r))
77 #define REG_WRITE(r, v) sys_write32((v), p->base_addr + (r))
97 #define MAC_CONF_ARPEN BIT(31)
99 #define MAC_CONF_IPC BIT(27)
101 #define MAC_CONF_GPSLCE BIT(23)
102 #define MAC_CONF_S2KP BIT(22)
103 #define MAC_CONF_CST BIT(21)
104 #define MAC_CONF_ACS BIT(20)
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| /Zephyr-Core-3.5.0/dts/riscv/ite/ |
| D | it82xx2.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
12 compatible = "mmio-sram";
16 intc: interrupt-controller@f03f00 {
17 compatible = "ite,it8xxx2-intc-v2";
18 #address-cells = <0>;
19 #interrupt-cells = <2>;
20 interrupt-controller;
25 compatible = "ite,it8xxx2-watchdog";
29 interrupt-parent = <&intc>;
32 gpiogcr: gpio-gcr@f03e00 {
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| /Zephyr-Core-3.5.0/modules/lvgl/ |
| D | lvgl_display_mono.c | 4 * SPDX-License-Identifier: Apache-2.0
13 uint16_t w = area->x2 - area->x1 + 1; in lvgl_flush_cb_mono()
14 uint16_t h = area->y2 - area->y1 + 1; in lvgl_flush_cb_mono()
15 struct lvgl_disp_data *data = (struct lvgl_disp_data *)disp_drv->user_data; in lvgl_flush_cb_mono()
16 const struct device *display_dev = data->display_dev; in lvgl_flush_cb_mono()
18 const bool is_epd = data->cap.screen_info & SCREEN_INFO_EPD; in lvgl_flush_cb_mono()
21 if (is_epd && !data->blanking_on && !is_last) { in lvgl_flush_cb_mono()
29 data->blanking_on = true; in lvgl_flush_cb_mono()
32 desc.buf_size = (w * h) / 8U; in lvgl_flush_cb_mono()
36 display_write(display_dev, area->x1, area->y1, &desc, (void *)color_p); in lvgl_flush_cb_mono()
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| /Zephyr-Core-3.5.0/subsys/fs/ext2/ |
| D | ext2_bitmap.c | 4 * SPDX-License-Identifier: Apache-2.0
20 LOG_DBG("Setting %d bit in bitmap", index); in ext2_bitmap_set()
22 uint32_t idx = index / 8; in ext2_bitmap_set()
23 uint32_t off = index % 8; in ext2_bitmap_set()
27 return -EINVAL; in ext2_bitmap_set()
30 __ASSERT((bm[idx] & BIT(off)) == 0, "Bit %d set in bitmap", index); in ext2_bitmap_set()
33 bm[idx] |= BIT(off); in ext2_bitmap_set()
41 LOG_DBG("Unsetting %d bit in bitmap", index); in ext2_bitmap_unset()
43 uint32_t idx = index / 8; in ext2_bitmap_unset()
44 uint32_t off = index % 8; in ext2_bitmap_unset()
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| /Zephyr-Core-3.5.0/dts/bindings/sensor/ |
| D | bosch,bmp388.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 200 - 200 - 5ms (default; chip reset value)
17 100 - 100 - 10ms
18 50 - 50 - 20ms
19 25 - 25 - 40ms
20 12.5 - 25/2 - 80ms
21 6.25 - 25/4 - 160ms
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| /Zephyr-Core-3.5.0/drivers/dai/intel/ssp/ |
| D | ssp.h | 4 * SPDX-License-Identifier: Apache-2.0
12 #include "dai-params-intel-ipc3.h"
13 #include "dai-params-intel-ipc4.h"
16 (((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo))
19 (((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo))
24 #define DAI_INTEL_SSP_IS_BIT_SET(reg, bit) (((reg >> bit) & (0x1)) != 0) argument
28 #define DAI_INTEL_SSP_MAX_FREQ_INDEX (DAI_INTEL_SSP_NUM_FREQ - 1)
35 #define DAI_INTEL_SSP_FIFO_WATERMARK 8
42 #define DAI_INTEL_SSP_DEFAULT_TRY_TIMES 8
65 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/ |
| D | pmc_interface.h | 2 * SPDX-License-Identifier: Apache-2.0
18 * The requesting agent will write the PMC command op-code into this field.
29 * Some commands require additional information which is passed into this 8 bit field.
31 #define CW_PMC_IPC_PARAM1 GENMASK(15, 8)
34 * Some commands require additional information which is passed into this 8 bit field.
39 * Some commands require additional information which is passed into this 4 bit field.
49 * busy - The run/busy bit can only be set by the requesting agent and can only be cleared by the
50 * responding agent. When this bit is set it will prompt the PMC to execute the command placed in
55 #define CW_PMC_IPC_BUSY BIT(31)
61 * No operation - PMC FW will clear the run / busy bit and return a success response
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| /Zephyr-Core-3.5.0/include/zephyr/sys/ |
| D | byteorder.h | 6 * Copyright (c) 2015-2016, Intel Corporation.
8 * SPDX-License-Identifier: Apache-2.0
20 #define __bswap_16(x) ((uint16_t) ((((x) >> 8) & 0xff) | (((x) & 0xff) << 8)))
25 (((x) >> 8) & 0xff00) | \
26 (((x) & 0xff00) << 8) | \
30 (((x) >> 8) & 0xff0000) | \
31 (((x) & 0xff0000) << 8) | \
37 (((x) >> 8) & 0xff000000) | \
38 (((x) & 0xff000000) << 8) | \
44 * @brief Convert 16-bit integer from little-endian to host endianness.
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| /Zephyr-Core-3.5.0/tests/drivers/can/api/src/ |
| D | common.c | 5 * SPDX-License-Identifier: Apache-2.0
24 * @brief Standard (11-bit) CAN ID frame 1.
29 .dlc = 8,
30 .data = {1, 2, 3, 4, 5, 6, 7, 8}
34 * @brief Standard (11-bit) CAN ID frame 2.
39 .dlc = 8,
40 .data = {1, 2, 3, 4, 5, 6, 7, 8}
44 * @brief Extended (29-bit) CAN ID frame 1.
49 .dlc = 8,
50 .data = {1, 2, 3, 4, 5, 6, 7, 8}
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| /Zephyr-Core-3.5.0/dts/bindings/dma/ |
| D | gd,gd32-dma-v1.yaml | 2 # SPDX-License-Identifier: Apache-2.0
11 config: A 32bit mask specifying the DMA channel configuration
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
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| /Zephyr-Core-3.5.0/drivers/i2c/ |
| D | i2c_andes_atciic100.h | 4 * SPDX-License-Identifier: Apache-2.0
32 ((const struct i2c_atciic100_config * const)(dev)->config)->base
44 #define DATA_MSK BIT_MASK(8)
48 #define IEN_CMPL BIT(9)
49 #define IEN_BYTE_RECV BIT(8)
50 #define IEN_BYTE_TRANS BIT(7)
51 #define IEN_START BIT(6)
52 #define IEN_STOP BIT(5)
53 #define IEN_ARB_LOSE BIT(4)
54 #define IEN_ADDR_HIT BIT(3)
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