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40 /* Select Q divisor to produce vco on [384 MHz, 768 MHz]. */ in soc_early_init_hook()41 if (MHZ(768) / 8 >= CORECLK_HZ) { in soc_early_init_hook()43 } else if (MHZ(768) / 4 >= CORECLK_HZ) { in soc_early_init_hook()
26 reg = <0x330000 DT_SIZE_K(768)>;36 reg = <0x700000 DT_SIZE_K(768)>;
8 CONFIG_BT_DEVICE_APPEARANCE=768
9 CONFIG_BT_DEVICE_APPEARANCE=768
54 [00:00:02.780,000] <inf> main: RGBP width [1024; 1024; 0] height [768; 768; 0]64 [00:00:02.780,000] <inf> main: JPEG width [1024; 1024; 0] height [768; 768; 0]
8 CONFIG_LOG_BUFFER_SIZE=768
11 CONFIG_ISR_STACK_SIZE=768
6 flash: 768
9 ram: 768
5 ram: 768
14 ram: 768
10 flash: 768
1 CONFIG_ISR_STACK_SIZE=768
8 CONFIG_ISR_STACK_SIZE=768
15 ram: 768
19 default 768
2 CONFIG_ISR_STACK_SIZE=768
20 CONFIG_SHELL_STACK_SIZE=768
12 reg = <0x20000000 DT_SIZE_K(768)>;
