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/Zephyr-Core-3.6.0/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/
Dservice_a_1.c45 '6', '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8',
49 '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8', '8', '9',
53 '7', '7', '7', '7', '7', '8', '8', '8', '8', '8', '9', '9', '9',
56 '4', '5', '5', '5', '5', '5', '6', '6', '6', '6', '6', '7', '7',
57 '7', '7', '7', '8', '8', '8', '8', '8', '9', '9', '9', '9', '9',
60 '5', '5', '5', '5', '6', '6', '6', '6', '6', '7', '7', '7', '7',
61 '7', '8', '8', '8', '8', '8', '9', '9', '9', '9', '9', '0', '0',
64 '5', '5', '6', '6', '6', '6', '6', '7', '7', '7', '7', '7', '8',
68 '6', '6', '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8',
72 '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8', '8',
[all …]
/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/clock/
Dstm32h5_clock.h61 * - reg (1/2/3/4/5) [ 0 : 7 ]
64 * - val (0..7) [ 16 : 18 ]
69 * @param val Clock value (0, 1, ... 7).
89 #define USART1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR1_REG)
90 #define USART2_SEL(val) STM32_CLOCK(val, 7, 3, CCIPR1_REG)
91 #define USART3_SEL(val) STM32_CLOCK(val, 7, 6, CCIPR1_REG)
92 #define USART4_SEL(val) STM32_CLOCK(val, 7, 9, CCIPR1_REG)
93 #define USART5_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR1_REG)
94 #define USART6_SEL(val) STM32_CLOCK(val, 7, 15, CCIPR1_REG)
95 #define USART7_SEL(val) STM32_CLOCK(val, 7, 18, CCIPR1_REG)
[all …]
/Zephyr-Core-3.6.0/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-miwus-wui-map.dtsi18 wui_ioe7: wui0-8-7 {
19 miwus = <&miwu0 7 7>; /* GPIOE7 */
29 wui_io66: wui1-7-6 {
64 wui_lct: wui2-6-7 {
65 miwus = <&miwu2 5 7>; /* LCT Event */
69 wui_cr_sin2: wui2-7-3 {
72 wui_cr_sin3: wui2-7-4 {
75 wui_cr_sin4: wui2-7-5 {
78 wui_i3c1_addrw: wui2-7-6 {
81 wui_i3c1_rstw: wui2-7-7 {
[all …]
Dnpcx4-lvol-ctrl-map.dtsi17 lvols = <&scfg 1 7>;
36 lvols = <&scfg 5 7>;
62 lvols = <&scfg 6 7>;
65 /* Low-Voltage IO Control 7 */
67 lvols = <&scfg 7 0>;
70 lvols = <&scfg 7 1>;
73 lvols = <&scfg 7 2>;
76 lvols = <&scfg 7 3>;
79 lvols = <&scfg 7 4>;
82 lvols = <&scfg 7 5>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/nuvoton/npcx/
Dnpcx-miwus-wui-map.dtsi26 wui_io87: wui0-1-7 {
27 miwus = <&miwu0 0 7>; /* GPIO87 */
52 wui_t0out: wui0-2-7 {
53 miwus = <&miwu0 1 7>; /* T0OUT */
78 wui_ioa5: wui0-3-7 {
79 miwus = <&miwu0 2 7>; /* GPIOA5 */
104 wui_mtc: wui0-4-7 {
105 miwus = <&miwu0 3 7>; /* MTC */
130 wui_plt_rst: wui0-5-7 {
131 miwus = <&miwu0 4 7>; /* PLT_RST */
[all …]
/Zephyr-Core-3.6.0/boards/arm/lpcxpresso55s69/
Dpinmux.c19 * Flexcomm 6 and 7 are connected to codec on board, and shared signal in lpcxpresso_55s69_pinmux_init()
24 /* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm 7 */ in lpcxpresso_55s69_pinmux_init()
25 SYSCTL->SHAREDCTRLSET[0] = SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(7) | in lpcxpresso_55s69_pinmux_init()
26 SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(7); in lpcxpresso_55s69_pinmux_init()
29 /* Select Data in from Transmit I2S - Flexcomm 7 */ in lpcxpresso_55s69_pinmux_init()
30 SYSCTL->SHAREDCTRLSET[0] |= SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(7); in lpcxpresso_55s69_pinmux_init()
31 /* Enable Transmit I2S - Flexcomm 7 for Shared Data Out */ in lpcxpresso_55s69_pinmux_init()
39 /* Set Transmit I2S - Flexcomm 7 SCK, WS from shared signal set 0 */ in lpcxpresso_55s69_pinmux_init()
40 SYSCTL->FCCTRLSEL[7] = SYSCTL_FCCTRLSEL_SCKINSEL(1) | in lpcxpresso_55s69_pinmux_init()
46 /* Select Transmit I2S - Flexcomm 7 Data out to shared signal set 0 */ in lpcxpresso_55s69_pinmux_init()
[all …]
/Zephyr-Core-3.6.0/tests/net/traffic_class/
Dtestcase.yaml37 net.traffic_class.7:
39 - CONFIG_NET_TC_TX_COUNT=7
40 - CONFIG_NET_TC_RX_COUNT=7
66 net.traffic_class.7_no_rx:
68 - CONFIG_NET_TC_TX_COUNT=7
95 net.traffic_class.7_no_tx:
97 - CONFIG_NET_TC_RX_COUNT=7
119 - CONFIG_NET_TC_TX_COUNT=7
127 - CONFIG_NET_TC_TX_COUNT=7
130 - CONFIG_NET_TC_RX_COUNT=7
[all …]
/Zephyr-Core-3.6.0/drivers/ieee802154/
Dieee802154_rf2xx_regs.h96 #define RF2XX_CCA_DONE 7
103 #define RF2XX_TRAC_BIT_MASK 7
106 #define RF2XX_TOM_EN 7
115 #define RF2XX_PA_EXT_EN 7
124 #define RF2XX_PA_BOOST 7
131 #define RF2XX_RX_CRC_VALID 7
137 #define RF2XX_CCA_REQUEST 7
151 #define RF2XX_RX_SAFE_MODE 7
167 #define RF2XX_ANT_SEL 7
173 #define RF2XX_BAT_LOW 7
[all …]
/Zephyr-Core-3.6.0/drivers/pinctrl/
Dpinctrl_b91.c17 * gpio_en: PORT_A[0-7]
18 * gpio_en + 1*8: PORT_B[0-7]
19 * gpio_en + 2*8: PORT_C[0-7]
20 * gpio_en + 3*8: PORT_D[0-7]
21 * gpio_en + 4*8: PORT_E[0-7]
22 * gpio_en + 5*8: PORT_F[0-7]
31 * pin_mux + 1: PORT_A[4-7]
33 * pin_mux + 3: PORT_B[4-7]
35 * pin_mux + 5: PORT_C[4-7]
37 * pin_mux + 7: PORT_D[4-7]
[all …]
/Zephyr-Core-3.6.0/drivers/sensor/lsm6dsl/
Dlsm6dsl.h29 #define LSM6DSL_MASK_FUNC_CFG_EN BIT(7)
30 #define LSM6DSL_SHIFT_FUNC_CFG_EN 7
44 #define LSM6DSL_MASK_FIFO_CTRL1_FTH (BIT(7) | BIT(6) | \
51 #define LSM6DSL_MASK_FIFO_CTRL2_TIMER_PEDO_FIFO_EN BIT(7)
52 #define LSM6DSL_SHIFT_FIFO_CTRL2_TIMER_PEDO_FIFO_EN 7
70 #define LSM6DSL_MASK_FIFO_CTRL4_STOP_ON_FTH BIT(7)
71 #define LSM6DSL_SHIFT_FIFO_CTRL4_STOP_ON_FTH 7
90 #define LSM6DSL_MASK_DRDY_PULSE_CFG_G_DRDY_PULSED BIT(7)
91 #define LSM6DSL_SHIFT_DRDY_PULSE_CFG_G_DRDY_PULSED 7
96 #define LSM6DSL_MASK_INT1_CTRL_STEP_DETECTOR BIT(7)
[all …]
/Zephyr-Core-3.6.0/drivers/audio/
Dtlv320dac310x.h22 #define NDAC_POWER_UP BIT(7)
23 #define NDAC_POWER_UP_MASK BIT(7)
24 #define NDAC_DIV_MASK BIT_MASK(7)
28 #define MDAC_POWER_UP BIT(7)
29 #define MDAC_POWER_UP_MASK BIT(7)
30 #define MDAC_DIV_MASK BIT_MASK(7)
61 #define BCLK_DIV_POWER_UP BIT(7)
62 #define BCLK_DIV_POWER_UP_MASK BIT(7)
63 #define BCLK_DIV_MASK BIT_MASK(7)
73 #define DAC_LR_POWERUP_DEFAULT (BIT(7) | BIT(6) | BIT(4) | BIT(2))
[all …]
/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/pinctrl/
Dti-cc32xx-pinctrl.h18 * - 7..5: Drive strength.
56 #define UART1_TX_P1 TI_CC32XX_PINMUX(1U, 7U)
65 #define UART1_RX_P2 TI_CC32XX_PINMUX(2U, 7U)
73 #define UART0_TX_P3 TI_CC32XX_PINMUX(3U, 7U)
79 #define UART0_RX_P4 TI_CC32XX_PINMUX(4U, 7U)
84 #define GSPI_CLK_P5 TI_CC32XX_PINMUX(5U, 7U)
90 #define GSPI_MISO_P6 TI_CC32XX_PINMUX(6U, 7U)
95 #define GPIO16_P7 TI_CC32XX_PINMUX(7U, 0U)
96 #define GSPI_MOSI_P7 TI_CC32XX_PINMUX(7U, 7U)
97 #define PDATA10_P7 TI_CC32XX_PINMUX(7U, 4U)
[all …]
Dambiq-apollo4-pinctrl.h26 #define NCE0_P0 APOLLO4_PINMUX(0, 7)
37 #define NCE1_P1 APOLLO4_PINMUX(1, 7)
49 #define NCE2_P2 APOLLO4_PINMUX(2, 7)
61 #define NCE3_P3 APOLLO4_PINMUX(3, 7)
72 #define NCE4_P4 APOLLO4_PINMUX(4, 7)
88 #define NCE5_P5 APOLLO4_PINMUX(5, 7)
103 #define NCE6_P6 APOLLO4_PINMUX(6, 7)
109 #define M0MISO_P7 APOLLO4_PINMUX(7, 0)
110 #define TRIG0_P7 APOLLO4_PINMUX(7, 1)
111 #define I2S0_WS_P7 APOLLO4_PINMUX(7, 2)
[all …]
/Zephyr-Core-3.6.0/drivers/charger/
Dbq24190.h12 #define BQ24190_REG_ISC_EN_HIZ_MASK BIT(7)
13 #define BQ24190_REG_ISC_EN_HIZ_SHIFT 7
20 #define BQ24190_REG_POC_RESET_MASK BIT(7)
21 #define BQ24190_REG_POC_RESET_SHIFT 7
40 #define BQ24190_REG_CCC_ICHG_MASK GENMASK(7, 2)
51 #define BQ24190_REG_PCTCC_IPRECHG_MASK GENMASK(7, 4)
66 #define BQ24190_REG_CVC_VREG_MASK GENMASK(7, 2)
79 #define BQ24190_REG_CTTC_EN_TERM_MASK BIT(7)
80 #define BQ24190_REG_CTTC_EN_TERM_SHIFT 7
94 #define BQ24190_REG_ICTRC_BAT_COMP_MASK GENMASK(7, 5)
[all …]
/Zephyr-Core-3.6.0/samples/subsys/nvs/
Dsample.yaml19 - "Id: 5, Longarray: 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b \
23 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f"
/Zephyr-Core-3.6.0/boards/riscv/adp_xc7k_ae350/
Dadp_xc7k_ae350.dts38 label = "7SEG LED1 A";
42 label = "7SEG LED1 B";
46 label = "7SEG LED1 C";
50 label = "7SEG LED1 D";
54 label = "7SEG LED1 E";
58 label = "7SEG LED1 F";
62 label = "7SEG LED1 G";
66 label = "7SEG LED1 DP";
71 label = "7SEG LED2 A";
75 label = "7SEG LED2 B";
[all …]
/Zephyr-Core-3.6.0/samples/net/wifi/boards/
Desp32s2_saola.conf5 CONFIG_NET_PKT_RX_COUNT=7
6 CONFIG_NET_PKT_TX_COUNT=7
7 CONFIG_NET_BUF_RX_COUNT=7
8 CONFIG_NET_BUF_TX_COUNT=7
/Zephyr-Core-3.6.0/soc/arm/renesas_rcar/gen4/
Dpfc_r8a779f0.c15 { RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */
46 { RCAR_GP_PIN(1, 7), 28, 3 }, /* GP1_07 */
83 { RCAR_GP_PIN(2, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */
110 { RCAR_GP_PIN(3, 7), 28, 3 }, /* TSN2_LINK_B */
139 { RCAR_GP_PIN(4, 7), 28, 3 }, /* GP4_07 */
182 { RCAR_GP_PIN(5, 7), 28, 3 }, /* ETNB0RXD3 */
212 { RCAR_GP_PIN(6, 7), 28, 3 }, /* RLIN34RX/INTP20 */
248 { RCAR_GP_PIN(7, 7), 28, 3 }, /* CAN3RX/INTP3 */
249 { RCAR_GP_PIN(7, 6), 24, 3 }, /* CAN3TX */
250 { RCAR_GP_PIN(7, 5), 20, 3 }, /* CAN2RX/INTP2 */
[all …]
/Zephyr-Core-3.6.0/soc/arm/xilinx_zynq7000/xc7zxxx/
DKconfig.soc16 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
22 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
29 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
35 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
42 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
49 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
56 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
/Zephyr-Core-3.6.0/tests/lib/cmsis_dsp/statistics/src/
Dq15.c37 DEFINE_TEST_VARIANT3(statistics_q15, arm_max_q15, 7, in_com1, 0, 7);
58 DEFINE_TEST_VARIANT3(statistics_q15, arm_min_q15, 7, in_com1, 0, 7);
79 DEFINE_TEST_VARIANT3(statistics_q15, arm_absmax_q15, 7, in_absminmax, 0, 7);
100 DEFINE_TEST_VARIANT3(statistics_q15, arm_absmin_q15, 7, in_absminmax, 0, 7);
133 DEFINE_TEST_VARIANT3(statistics_q15, arm_mean_q15, 7, in_com2, 0, 7);
166 DEFINE_TEST_VARIANT3(statistics_q15, arm_power_q15, 7, in_com1, 0, 7);
199 DEFINE_TEST_VARIANT3(statistics_q15, arm_rms_q15, 7, in_com1, 0, 7);
232 DEFINE_TEST_VARIANT3(statistics_q15, arm_std_q15, 7, in_com1, 0, 7);
265 DEFINE_TEST_VARIANT3(statistics_q15, arm_var_q15, 7, in_com1, 0, 7);
/Zephyr-Core-3.6.0/dts/bindings/clock/
Dnuvoton,npcx-pcc.yaml67 7, CORE_CLK = OFMCLK / 7
78 - 7
98 7, APB1_CLK = OFMCLK / 7
109 - 7
129 7, APB2_CLK = OFMCLK / 7
140 - 7
160 7, APB3_CLK = OFMCLK / 7
171 - 7
190 7, APB4_CLK = OFMCLK / 7
201 - 7
/Zephyr-Core-3.6.0/tests/bluetooth/qualification/
DICS_Zephyr_Bluetooth_Controller_nrf52dk_nrf52832.pts84 <row>7</row>
116 <row>7</row>
252 <row>7</row>
255 <table>7</table>
259 <table>7</table>
263 <table>7</table>
267 <table>7</table>
271 <table>7</table>
275 <table>7</table>
279 <table>7</table>
[all …]
DProject_Zephyr_Bluetooth_Controller_nrf52dk_nrf52832.bls87 <row>7</row>
119 <row>7</row>
255 <row>7</row>
258 <table>7</table>
262 <table>7</table>
266 <table>7</table>
270 <table>7</table>
274 <table>7</table>
278 <table>7</table>
282 <table>7</table>
[all …]
/Zephyr-Core-3.6.0/drivers/sensor/lsm9ds0_gyro/
Dlsm9ds0_gyro.h23 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6))
43 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I1_INT1 BIT(7)
44 #define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I1_INT1 7
61 #define LSM9DS0_GYRO_MASK_CTRL_REG4_G_BDU BIT(7)
62 #define LSM9DS0_GYRO_SHIFT_CTRL_REG4_G_BDU 7
71 #define LSM9DS0_GYRO_MASK_CTRL_REG5_G_BOOT BIT(7)
72 #define LSM9DS0_GYRO_SHIFT_CTRL_REG5_G_BOOT 7
85 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_ZYXOR BIT(7)
86 #define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_ZYXOR 7
110 #define LSM9DS0_GYRO_MASK_FIFO_CTRL_REG_G_FM (BIT(7) | BIT(6) | BIT(5))
[all …]
/Zephyr-Core-3.6.0/boards/riscv/litex_vexriscv/doc/img/
Dsymbiflow.svg1 …7 .5 9.9 1.6 2.9 1.1 5.4 2.6 7.4 4.5s3.6 4.2 4.7 6.8c1.1 2.6 1.7 5.5 1.7 8.6L56.4 48c0-2.7-.8-4.9-…

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