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/Zephyr-Core-2.7.6/tests/bluetooth/bsim_bt/edtt_ble_test_app/gatt_test_app/src/gatt/
Dservice_a_1.c45 '6', '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8',
49 '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8', '8', '9',
53 '7', '7', '7', '7', '7', '8', '8', '8', '8', '8', '9', '9', '9',
56 '4', '5', '5', '5', '5', '5', '6', '6', '6', '6', '6', '7', '7',
57 '7', '7', '7', '8', '8', '8', '8', '8', '9', '9', '9', '9', '9',
60 '5', '5', '5', '5', '6', '6', '6', '6', '6', '7', '7', '7', '7',
61 '7', '8', '8', '8', '8', '8', '9', '9', '9', '9', '9', '0', '0',
64 '5', '5', '6', '6', '6', '6', '6', '7', '7', '7', '7', '7', '8',
68 '6', '6', '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8',
72 '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8', '8',
[all …]
/Zephyr-Core-2.7.6/dts/arm/nuvoton/npcx/
Dnpcx-miwus-wui-map.dtsi29 wui_io87: wui0-1-7 {
30 miwus = <&miwu0 0 7>; /* GPIO87 */
55 wui_t0out: wui0-2-7 {
56 miwus = <&miwu0 1 7>; /* T0OUT */
81 wui_ioa5: wui0-3-7 {
82 miwus = <&miwu0 2 7>; /* GPIOA5 */
107 wui_mtc: wui0-4-7 {
108 miwus = <&miwu0 3 7>; /* MTC */
133 wui_plt_rst: wui0-5-7 {
134 miwus = <&miwu0 4 7>; /* PLT_RST */
[all …]
/Zephyr-Core-2.7.6/tests/net/traffic_class/
Dtestcase.yaml29 net.traffic_class.7:
31 - CONFIG_NET_TC_TX_COUNT=7
32 - CONFIG_NET_TC_RX_COUNT=7
58 net.traffic_class.7_no_rx:
60 - CONFIG_NET_TC_TX_COUNT=7
87 net.traffic_class.7_no_tx:
89 - CONFIG_NET_TC_RX_COUNT=7
111 - CONFIG_NET_TC_TX_COUNT=7
119 - CONFIG_NET_TC_TX_COUNT=7
122 - CONFIG_NET_TC_RX_COUNT=7
[all …]
/Zephyr-Core-2.7.6/drivers/ieee802154/
Dieee802154_rf2xx_regs.h90 #define RF2XX_CCA_DONE 7
99 #define RF2XX_TOM_EN 7
108 #define RF2XX_PA_EXT_EN 7
117 #define RF2XX_PA_BOOST 7
124 #define RF2XX_RX_CRC_VALID 7
129 #define RF2XX_CCA_REQUEST 7
143 #define RF2XX_RX_SAFE_MODE 7
153 #define RF2XX_ANT_SEL 7
159 #define RF2XX_BAT_LOW 7
169 #define RF2XX_AVREG_EXT 7
[all …]
/Zephyr-Core-2.7.6/boards/riscv/adp_xc7k_ae350/
Dadp_xc7k_ae350.dts33 label = "7SEG LED1 A";
37 label = "7SEG LED1 B";
41 label = "7SEG LED1 C";
45 label = "7SEG LED1 D";
49 label = "7SEG LED1 E";
53 label = "7SEG LED1 F";
57 label = "7SEG LED1 G";
61 label = "7SEG LED1 DP";
66 label = "7SEG LED2 A";
70 label = "7SEG LED2 B";
[all …]
/Zephyr-Core-2.7.6/drivers/sensor/lsm6dsl/
Dlsm6dsl.h28 #define LSM6DSL_MASK_FUNC_CFG_EN BIT(7)
29 #define LSM6DSL_SHIFT_FUNC_CFG_EN 7
43 #define LSM6DSL_MASK_FIFO_CTRL1_FTH (BIT(7) | BIT(6) | \
50 #define LSM6DSL_MASK_FIFO_CTRL2_TIMER_PEDO_FIFO_EN BIT(7)
51 #define LSM6DSL_SHIFT_FIFO_CTRL2_TIMER_PEDO_FIFO_EN 7
69 #define LSM6DSL_MASK_FIFO_CTRL4_STOP_ON_FTH BIT(7)
70 #define LSM6DSL_SHIFT_FIFO_CTRL4_STOP_ON_FTH 7
89 #define LSM6DSL_MASK_DRDY_PULSE_CFG_G_DRDY_PULSED BIT(7)
90 #define LSM6DSL_SHIFT_DRDY_PULSE_CFG_G_DRDY_PULSED 7
95 #define LSM6DSL_MASK_INT1_CTRL_STEP_DETECTOR BIT(7)
[all …]
/Zephyr-Core-2.7.6/drivers/audio/
Dtlv320dac310x.h22 #define NDAC_POWER_UP BIT(7)
23 #define NDAC_POWER_UP_MASK BIT(7)
24 #define NDAC_DIV_MASK BIT_MASK(7)
28 #define MDAC_POWER_UP BIT(7)
29 #define MDAC_POWER_UP_MASK BIT(7)
30 #define MDAC_DIV_MASK BIT_MASK(7)
61 #define BCLK_DIV_POWER_UP BIT(7)
62 #define BCLK_DIV_POWER_UP_MASK BIT(7)
63 #define BCLK_DIV_MASK BIT_MASK(7)
73 #define DAC_LR_POWERUP_DEFAULT (BIT(7) | BIT(6) | BIT(4) | BIT(2))
[all …]
/Zephyr-Core-2.7.6/samples/subsys/nvs/
Dsample.yaml17 …7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a…
/Zephyr-Core-2.7.6/drivers/pinmux/
Dpinmux_b91.c16 * gpio_en: PORT_A[0-7]
17 * gpio_en + 1*8: PORT_B[0-7]
18 * gpio_en + 2*8: PORT_C[0-7]
19 * gpio_en + 3*8: PORT_D[0-7]
20 * gpio_en + 4*8: PORT_E[0-7]
21 * gpio_en + 5*8: PORT_F[0-7]
30 * pin_mux + 1: PORT_A[4-7]
32 * pin_mux + 3: PORT_B[4-7]
34 * pin_mux + 5: PORT_C[4-7]
36 * pin_mux + 7: PORT_D[4-7]
[all …]
/Zephyr-Core-2.7.6/dts/bindings/clock/
Dnuvoton,npcx-pcc.yaml69 7, CORE_CLK = OFMCLK / 7
80 - 7
100 7, APB1_CLK = OFMCLK / 7
111 - 7
131 7, APB2_CLK = OFMCLK / 7
142 - 7
162 7, APB3_CLK = OFMCLK / 7
173 - 7
193 7, APB4_CLK = OFMCLK / 7
204 - 7
/Zephyr-Core-2.7.6/modules/hal_nordic/nrfx/
Dnrfx_config_nrf52805.h61 // <7=> 7
64 #define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
93 // <7=> Cyan
109 // <7=> Cyan
147 // <7=> 7
150 #define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7
174 // <7=> 7
177 #define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY 7
206 // <7=> Cyan
222 // <7=> Cyan
[all …]
Dnrfx_config_nrf52840.h62 // <7=> 7
65 #define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
94 // <7=> Cyan
110 // <7=> Cyan
136 // <7=> 7
139 #define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
168 // <7=> Cyan
184 // <7=> Cyan
246 // <7=> 7
249 #define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7
[all …]
Dnrfx_config_nrf52833.h62 // <7=> 7
65 #define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
94 // <7=> Cyan
110 // <7=> Cyan
136 // <7=> 7
139 #define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
168 // <7=> Cyan
184 // <7=> Cyan
246 // <7=> 7
249 #define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7
[all …]
Dnrfx_config_nrf52810.h61 // <7=> 7
64 #define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
93 // <7=> Cyan
109 // <7=> Cyan
135 // <7=> 7
138 #define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
167 // <7=> Cyan
183 // <7=> Cyan
221 // <7=> 7
224 #define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7
[all …]
Dnrfx_config_nrf52811.h62 // <7=> 7
65 #define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
94 // <7=> Cyan
110 // <7=> Cyan
136 // <7=> 7
139 #define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
168 // <7=> Cyan
184 // <7=> Cyan
222 // <7=> 7
225 #define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7
[all …]
Dnrfx_config_nrf52820.h62 // <7=> 7
65 #define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
94 // <7=> Cyan
110 // <7=> Cyan
136 // <7=> 7
139 #define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
168 // <7=> Cyan
184 // <7=> Cyan
246 // <7=> 7
249 #define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7
[all …]
Dnrfx_config_nrf52832.h62 // <7=> 7
65 #define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
94 // <7=> Cyan
110 // <7=> Cyan
136 // <7=> 7
139 #define NRFX_COMP_DEFAULT_CONFIG_IRQ_PRIORITY 7
168 // <7=> Cyan
184 // <7=> Cyan
246 // <7=> 7
249 #define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7
[all …]
/Zephyr-Core-2.7.6/drivers/sensor/lsm9ds0_gyro/
Dlsm9ds0_gyro.h22 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6))
42 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I1_INT1 BIT(7)
43 #define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I1_INT1 7
60 #define LSM9DS0_GYRO_MASK_CTRL_REG4_G_BDU BIT(7)
61 #define LSM9DS0_GYRO_SHIFT_CTRL_REG4_G_BDU 7
70 #define LSM9DS0_GYRO_MASK_CTRL_REG5_G_BOOT BIT(7)
71 #define LSM9DS0_GYRO_SHIFT_CTRL_REG5_G_BOOT 7
84 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_ZYXOR BIT(7)
85 #define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_ZYXOR 7
109 #define LSM9DS0_GYRO_MASK_FIFO_CTRL_REG_G_FM (BIT(7) | BIT(6) | BIT(5))
[all …]
/Zephyr-Core-2.7.6/boards/riscv/litex_vexriscv/doc/img/
Dsymbiflow.svg1 …7 .5 9.9 1.6 2.9 1.1 5.4 2.6 7.4 4.5s3.6 4.2 4.7 6.8c1.1 2.6 1.7 5.5 1.7 8.6L56.4 48c0-2.7-.8-4.9-…
/Zephyr-Core-2.7.6/drivers/sensor/max30101/
DKconfig14 range 0 7
27 7 = 32 samples
81 range 0 7
95 7 = 3200 Hz
143 range 0 7
154 7: LED3 (green), PILOT_PA
158 range 0 7
169 7: LED3 (green), PILOT_PA
173 range 0 7
184 7: LED3 (green), PILOT_PA
[all …]
/Zephyr-Core-2.7.6/tests/lib/cmsis_dsp/statistics/src/
Dq15.c37 DEFINE_TEST_VARIANT3(arm_max_q15, 7, in_com1, 0, 7);
58 DEFINE_TEST_VARIANT3(arm_min_q15, 7, in_com1, 0, 7);
79 DEFINE_TEST_VARIANT3(arm_absmax_q15, 7, in_absminmax, 0, 7);
100 DEFINE_TEST_VARIANT3(arm_absmin_q15, 7, in_absminmax, 0, 7);
133 DEFINE_TEST_VARIANT3(arm_mean_q15, 7, in_com2, 0, 7);
166 DEFINE_TEST_VARIANT3(arm_power_q15, 7, in_com1, 0, 7);
199 DEFINE_TEST_VARIANT3(arm_rms_q15, 7, in_com1, 0, 7);
232 DEFINE_TEST_VARIANT3(arm_std_q15, 7, in_com1, 0, 7);
265 DEFINE_TEST_VARIANT3(arm_var_q15, 7, in_com1, 0, 7);
/Zephyr-Core-2.7.6/drivers/sensor/lsm9ds0_mfd/
Dlsm9ds0_mfd.h21 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMOR BIT(7)
22 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_ZYXMOR 7
49 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_XMIEN BIT(7)
50 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_XMIEN 7
67 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_PTH_X BIT(7)
68 #define LSM9DS0_MFD_SHIFT_INT_SRC_REG_M_M_PTH_X 7
98 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_BOOT BIT(7)
99 #define LSM9DS0_MFD_SHIFT_CTRL_REG0_XM_BOOT 7
112 #define LSM9DS0_MFD_MASK_CTRL_REG1_XM_AODR (BIT(7) | BIT(6) | BIT(5) | \
125 #define LSM9DS0_MFD_MASK_CTRL_REG2_XM_ABW (BIT(7) | BIT(6))
[all …]
/Zephyr-Core-2.7.6/drivers/gpio/
Dgpio_ite_it8xxx2.c128 [IT8XXX2_IRQ_WU46] = {BIT(7), 4, BIT(6)},
136 [IT8XXX2_IRQ_WU57] = {BIT(7), 5, BIT(7)},
144 [IT8XXX2_IRQ_WU67] = {BIT(7), 6, BIT(7)},
145 [IT8XXX2_IRQ_WU70] = {BIT(0), 7, BIT(0)},
146 [IT8XXX2_IRQ_WU71] = {BIT(1), 7, BIT(1)},
147 [IT8XXX2_IRQ_WU72] = {BIT(2), 7, BIT(2)},
148 [IT8XXX2_IRQ_WU73] = {BIT(3), 7, BIT(3)},
149 [IT8XXX2_IRQ_WU74] = {BIT(4), 7, BIT(4)},
150 [IT8XXX2_IRQ_WU75] = {BIT(5), 7, BIT(5)},
151 [IT8XXX2_IRQ_WU76] = {BIT(6), 7, BIT(6)},
[all …]
/Zephyr-Core-2.7.6/drivers/sensor/lsm6ds0/
Dlsm6ds0.h19 #define LSM6DS0_MASK_ACT_THS_SLEEP_ON_INACT_EN BIT(7)
20 #define LSM6DS0_SHIFT_ACT_THS_SLEEP_ON_INACT_EN 7
29 #define LSM6DS0_MASK_INT_GEN_CFG_XL_AOI_XL BIT(7)
30 #define LSM6DS0_SHIFT_INT_GEN_CFG_XL_AOI_XL 7
53 #define LSM6DS0_MASK_INT_CTRL_INT_IG_G BIT(7)
54 #define LSM6DS0_SHIFT_INT_CTRL_INT_IG_G 7
74 #define LSM6DS0_MASK_CTRL_REG1_G_ODR_G (BIT(7) | BIT(6) | BIT(5))
88 #define LSM6DS0_MASK_CTRL_REG3_G_LP_MODE BIT(7)
89 #define LSM6DS0_SHIFT_CTRL_REG3_G_LP_MODE 7
161 #define LSM6DS0_MASK_CTRL_REG5_XL_DEC (BIT(7) | BIT(6))
[all …]
/Zephyr-Core-2.7.6/samples/subsys/usb/hid/
DREADME.rst38 usb 7-1: New USB device found, idVendor=2fe3, idProduct=0006, bcdDevice= 2.03
39 usb 7-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
40 usb 7-1: Product: Zephyr HID sample
41 usb 7-1: Manufacturer: ZEPHYR
42 usb 7-1: SerialNumber: 86FE679A598AC47A
43 …input: ZEPHYR Zephyr HID sample as /devices/platform/vhci_hcd.0/usb7/7-1/7-1:1.0/0003:2FE3:0100.00…

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