| /Zephyr-Core-3.5.0/drivers/pinctrl/ |
| D | pinctrl_b91.c | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/b91-pinctrl.h>
17 * gpio_en: PORT_A[0-7]
18 * gpio_en + 1*8: PORT_B[0-7]
19 * gpio_en + 2*8: PORT_C[0-7]
20 * gpio_en + 3*8: PORT_D[0-7]
21 * gpio_en + 4*8: PORT_E[0-7]
22 * gpio_en + 5*8: PORT_F[0-7]
24 #define reg_gpio_en(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, gpio_en) + \ argument
25 ((pin >> 8) * 8)))
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| D | pinctrl_ite_it8xxx2.c | 4 * SPDX-License-Identifier: Apache-2.0
21 /* gpio port control register (byte mapping to pin) */
43 * KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register
44 * (bit mapping to pin)
47 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port control register */
50 * KSO push-pull/open-drain bit of KSO[15:0] control register
55 * KSI/KSO pullup bit of KSI[7:0]/KSO[15:0] control register
71 const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config; in pinctrl_it8xxx2_set()
72 const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio); in pinctrl_it8xxx2_set()
73 uint32_t pincfg = pins->pincfg; in pinctrl_it8xxx2_set()
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| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | digilent,pmod.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 through 3 correspond to IO1 through IO4, and parent pins 4 through 7
9 correspond to IO5 through IO8, as depicted below for a 12-pin connector.
11 12-pin Pmod interface:
16 3 IO4 IO8 7
17 - GND GND -
18 - VDD VDD -
20 This binding can also be used with the 6-pin Pmod connector variant which
21 is a proper subset of the 12-pin connector. In that case parent pins 4
22 through 7 are omitted from the GPIO nexus node, resulting in a mapping
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| D | atmel-xplained-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained layout provide a standard 10 pin header. A board can have
12 every pin can be defined as general purpose GPIO.
29 https://www.microchip.com/development-tools/xplained-boards
30 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
36 Bind Pin Name Pin Pin Pin Name Bind
40 6 SPI(MISO) 7 8 SPI(SCK) 7
43 compatible: "atmel-xplained-header"
45 include: [gpio-nexus.yaml, base.yaml]
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| D | atmel-xplained-pro-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained Pro layout provide a standard 20 pin header. A board can have
9 names EXTn where n ϵ [1…7], n is determined by which ID pin is connected
28 https://www.microchip.com/development-tools/xplained-boards
29 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
35 Bind Pin Name Pin Pin Pin Name Bind
37 0 ADC(+) 3 4 ADC(-) 1
39 4 PWM(+) 7 8 PWM(-) 5
40 6 IRQ/GPIO3 9 10 SPI(CS1)/GPIO4 7
47 compatible: "atmel-xplained-pro-header"
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| D | seeed-xiao-header.yaml | 4 # SPDX-License-Identifier: Apache-2.0
12 Proceeding counter-clockwise:
13 * A 7-pin Digital/Analog Input header. This has input signals
15 * An 7-pin header Power and Digital/Analog Input header. This
17 top through 7 at the bottom.
22 0 D0 5V -
23 1 D1 GND -
24 2 D2 3V3 -
28 6 D6 D7 7
31 compatible: "seeed,xiao-gpio"
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| D | quicklogic,eos-s3-gpio.yaml | 3 compatible: "quicklogic,eos-s3-gpio"
5 include: [gpio-controller.yaml, base.yaml]
11 "#gpio-cells":
14 pin-secondary-config:
19 a primary(0) or a secondary(1) pin. EOS S3 supports up to 8 GPIOs
29 "7 : 23 / 45"
30 E.g. configuring GPIO 2 as secondary results in controlling pin 28,
32 "pin-secondary-config = <0x04>;"
34 gpio-cells:
35 - pin
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| D | particle-gen3-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 "shields" but use a different orientation and pin numbering scheme.
11 * A 12-pin header on the right. 9 pins on this header are exposed
13 * A 16-pin header. 13 pins on this header are exposed by this
17 0 through 8 correspond to the pins on the 12-pin header, starting
19 16-pin header, skipping the bottom pin then assigning 9 through 19,
20 skipping over GND, and replacing the lower 3V3 with pin 20. The
24 - 3V3
26 - GND
27 19 ADC0 LiPo+ -
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| D | ti,boosterpack-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
10 20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
11 10 x 2 pin headers. Both variants are compatible and stackable.
13 The pins of the 20 pin variant and the outer row of the 40 pin variant are
14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
23 7 SPI CLK 27 Analog 34 GPIO 14 SPI MISO
32 compatible: "ti,boosterpack-header"
34 include: [gpio-nexus.yaml, base.yaml]
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| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | nxp,s32ze-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The NXP S32 pin controller is a singleton node responsible for controlling
8 the pin function selection and pin properties. This node, labeled 'pinctrl' in
9 the SoC's devicetree, will define pin configurations in pin groups. Each group
10 within the pin configuration defines the pin configuration for a peripheral,
11 and each numbered subgroup in the pin group defines all the pins for that
20 #include <nxp/s32/S32Z27-BGA594-pinctrl.h>
26 output-enable;
30 input-enable;
35 The 'uart0_default' node contains the pin configurations for a particular state
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| D | ite,it8xxx2-pinctrl-func.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: ITE IT8XXX2 pin controller function node
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
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| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | gpio_kscan_ite_it8xxx2.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
21 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio output enable register (bit mapping to pin) */
23 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register (bit mapping to pin) */
25 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio data register (bit mapping to pin) */
27 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio data mirror register (bit mapping to pin) */
29 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio open drain register (bit mapping to pin) */
39 gpio_pin_t pin, in gpio_kscan_it8xxx2_configure() argument
42 const struct gpio_kscan_cfg *const config = dev->config; in gpio_kscan_it8xxx2_configure()
43 volatile uint8_t *reg_ksi_kso_gctrl = config->reg_ksi_kso_gctrl; in gpio_kscan_it8xxx2_configure()
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| D | gpio_ite_it8xxx2.c | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
12 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
35 /* gpio port data register (bit mapping to pin) */
37 /* gpio port control register (byte mapping to pin) */
39 /* gpio port data mirror register (bit mapping to pin) */
41 /* gpio port output type register (bit mapping to pin) */
57 ((struct gpio_ite_data *)(dev)->data)
60 ((const struct gpio_ite_cfg *)(dev)->config)
63 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/ |
| D | gecko-pinctrl.h | 3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
31 /** Position of the pin field. */
33 /** Mask for the pin field. */
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| D | ti-cc32xx-pinctrl.h | 3 * SPDX-License-Identifier: Apache-2.0
10 * The whole TI CC32XX pin configuration information is encoded in a 32-bit
13 * - 31..22: Reserved
14 * - 21..16: Pin.
15 * - 15..10: Reserved.
16 * - 9: Pull-down flag.
17 * - 8: Pull-up flag.
18 * - 7..5: Drive strength.
19 * - 4: Enable open-drain flag.
20 * - 3..0: Configuration mode
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| D | gecko-pinctrl-s1.h | 3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
31 /** Position of the pin field. */
33 /** Mask for the pin field. */
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| D | nrf-pinctrl.h | 3 * SPDX-License-Identifier: Apache-2.0
10 * The whole nRF pin configuration information is encoded in a 32-bit bitfield
13 * - 31..16: Pin function.
14 * - 15: Reserved.
15 * - 14: Pin inversion mode.
16 * - 13: Pin low power mode.
17 * - 12..9: Pin output drive configuration.
18 * - 8..7: Pin pull configuration.
19 * - 6..0: Pin number (combination of port and pin).
23 * @name nRF pin configuration bit field positions and masks.
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| D | rv32m1-pinctrl.h | 4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Specify PORTx->PCR register MUX field
14 * @param pin Port pin number (0 to 31)
15 * @param mux Alternate function number (0 to 7)
17 #define RV32M1_MUX(port, pin, mux) \ argument
18 (((((port) - 'A') & 0xF) << 28) | \
19 (((pin) & 0x3F) << 22) | \
|
| D | numicro-pinctrl.h | 4 * SPDX-License-Identifier: Apache-2.0
18 * @brief Pin configuration configuration bit field.
22 * - mfp [ 0 : 3 ]
23 * - pin [ 4 : 7 ]
24 * - port [ 8 : 11 ]
27 * @param pin Pin (0..15)
28 * @param mfp Multi-function value (0..15)
30 #define NUMICRO_PINMUX(port, pin, mfp) \ argument
31 (((((port) - 'A') & NUMICRO_PORT_MASK) << NUMICRO_PORT_SHIFT) | \
32 (((pin) & NUMICRO_PIN_MASK) << NUMICRO_PIN_SHIFT) | \
|
| /Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/common/ |
| D | Kconfig.soc | 2 # SPDX-License-Identifier: Apache-2.0
16 bool "Support for external, SPI-connected RAM"
66 bool "ESP-PSRAM16 or APS1604"
69 bool "ESP-PSRAM32 or IS25WP032"
72 bool "ESP-PSRAM64 or LY68L6400"
124 menu "PSRAM clock and cs IO for ESP32-DOWD"
132 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
140 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
142 endmenu # PSRAM clock and cs IO for ESP32-DOWD
144 menu "PSRAM clock and cs IO for ESP32-D2WD"
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| /Zephyr-Core-3.5.0/dts/bindings/sensor/ |
| D | st,ism330dhcx-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: sensor-device.yaml
7 drdy-gpios:
8 type: phandle-array
10 DRDY gpio pin
12 This pin defaults to active high when produced by the sensor.
16 int-pin:
20 Select DRDY pin number (1 or 2).
29 configuration at power-up.
31 - 1
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| /Zephyr-Core-3.5.0/drivers/smbus/ |
| D | intel_pch_smbus.h | 7 * PCH provides SMBus 2.0 - compliant Host Controller.
9 * SPDX-License-Identifier: Apache-2.0
17 /* Host Configuration (HCFG) - Offset 40h, 8 bits */
32 #define PCH_SMBUS_HSTS_BYTE_DONE BIT(7) /* Byte Done */
51 #define PCH_SMBUS_HCTL_CMD_BLOCK_PROC (7 << 2) /* Block Process cmd */
59 #define PCH_SMBUS_HCTL_PEC_EN BIT(7) /* Enable PEC */
67 #define PCH_SMBUS_TSA_ADDR_MASK GENMASK(7, 1) /* Address mask */
69 /* Set 7-bit address */
70 #define PCH_SMBUS_TSA_ADDR_SET(addr) (((addr) & BIT_MASK(7)) << 1)
73 #define PCH_SMBUS_TSA_ADDR_GET(reg) ((reg >> 1) & BIT_MASK(7))
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| /Zephyr-Core-3.5.0/tests/drivers/pinctrl/gd32/src/ |
| D | main_af.c | 3 * SPDX-License-Identifier: Apache-2.0
9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
19 zassert_equal(pcfg->state_cnt, 1U); in ZTEST()
21 scfg = &pcfg->states[0]; in ZTEST()
23 zassert_equal(scfg->id, PINCTRL_STATE_DEFAULT); in ZTEST()
24 zassert_equal(scfg->pin_cnt, 12U); in ZTEST()
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
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| D | main_afio.c | 3 * SPDX-License-Identifier: Apache-2.0
9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
19 zassert_equal(pcfg->state_cnt, 1U); in ZTEST()
21 scfg = &pcfg->states[0]; in ZTEST()
23 zassert_equal(scfg->id, PINCTRL_STATE_DEFAULT); in ZTEST()
24 zassert_equal(scfg->pin_cnt, 14U); in ZTEST()
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
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| /Zephyr-Core-3.5.0/drivers/sensor/fxas21002/ |
| D | Kconfig | 1 # FXAS21002 3-axis gyroscope
4 # SPDX-License-Identifier: Apache-2.0
23 pre-production devices can have a different value. It is unlikely you
32 0: +/-2000 dps (62.5 mdps/LSB)
33 1: +/-1000 dps (31.25 mdps/LSB)
34 2: +/-500 dps (15.625 mdps/LSB)
35 3: +/-250 dps (7.8125 mdps/LSB)
39 range 0 7
50 7: 12.5 Hz
75 bool "Data ready interrupt to INT1 pin"
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