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/Zephyr-latest/drivers/sensor/st/lsm6dsl/
Dlsm6dsl.h1 /* sensor_lsm6dsl.h - header file for LSM6DSL accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
29 #define LSM6DSL_MASK_FUNC_CFG_EN BIT(7)
30 #define LSM6DSL_SHIFT_FUNC_CFG_EN 7
31 #define LSM6DSL_MASK_FUNC_CFG_EN_B BIT(5)
35 #define LSM6DSL_MASK_SENSOR_SYNC_TIME_FRAME_TPH (BIT(3) | BIT(2) | \
36 BIT(1) | BIT(0))
40 #define LSM6DSL_MASK_SENSOR_SYNC_RES_RATIO (BIT(1) | BIT(0))
44 #define LSM6DSL_MASK_FIFO_CTRL1_FTH (BIT(7) | BIT(6) | \
45 BIT(5) | BIT(4) | \
[all …]
/Zephyr-latest/drivers/sensor/st/lsm9ds0_gyro/
Dlsm9ds0_gyro.h1 /* sensor_lsm9ds0_gyro.h - header file for LSM9DS0 gyroscope sensor driver */
6 * SPDX-License-Identifier: Apache-2.0
23 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6))
25 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_BW (BIT(5) | BIT(4))
27 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_PD BIT(3)
29 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_ZEN BIT(2)
31 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_XEN BIT(1)
33 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_YEN BIT(0)
37 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPM (BIT(5) | BIT(4))
39 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPCF (BIT(3) | BIT(2) | BIT(1) | \
[all …]
/Zephyr-latest/drivers/sensor/st/lps25hb/
Dlps25hb.h1 /* sensor_lps25hb.h - header file for LPS25HB pressure and temperature
8 * SPDX-License-Identifier: Apache-2.0
26 #define LPS25HB_MASK_RES_CONF_AVGT (BIT(3) | BIT(2))
28 #define LPS25HB_MASK_RES_CONF_AVGP (BIT(1) | BIT(0))
32 #define LPS25HB_MASK_CTRL_REG1_PD BIT(7)
33 #define LPS25HB_SHIFT_CTRL_REG1_PD 7
34 #define LPS25HB_MASK_CTRL_REG1_ODR (BIT(6) | BIT(5) | BIT(4))
36 #define LPS25HB_MASK_CTRL_REG1_DIFF_EN BIT(3)
38 #define LPS25HB_MASK_CTRL_REG1_BDU BIT(2)
40 #define LPS25HB_MASK_CTRL_REG1_RESET_AZ BIT(1)
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/Zephyr-latest/drivers/audio/
Dtas6422dac.h4 * SPDX-License-Identifier: Apache-2.0
18 #define MODE_CTRL_RESET BIT(7)
19 #define MODE_CTRL_RESET_MASK BIT(7)
20 #define MODE_CTRL_PBTL_CH12 BIT(4)
21 #define MODE_CTRL_PBTL_CH12_MASK BIT(4)
22 #define MODE_CTRL_CH1_LO_MODE BIT(3)
23 #define MODE_CTRL_CH1_LO_MODE_MASK BIT(3)
24 #define MODE_CTRL_CH2_LO_MODE BIT(2)
25 #define MODE_CTRL_CH2_LO_MODE_MASK BIT(2)
29 #define MISC_CTRL_1_HPF_BYPASS BIT(7)
[all …]
Dtlv320dac310x.h4 * SPDX-License-Identifier: Apache-2.0
22 #define NDAC_POWER_UP BIT(7)
23 #define NDAC_POWER_UP_MASK BIT(7)
24 #define NDAC_DIV_MASK BIT_MASK(7)
28 #define MDAC_POWER_UP BIT(7)
29 #define MDAC_POWER_UP_MASK BIT(7)
30 #define MDAC_DIV_MASK BIT_MASK(7)
57 #define IF_CTRL_BCLK_OUT BIT(3)
58 #define IF_CTRL_WCLK_OUT BIT(2)
61 #define BCLK_DIV_POWER_UP BIT(7)
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/Zephyr-latest/drivers/charger/
Dbq24190.h4 * SPDX-License-Identifier: Apache-2.0
12 #define BQ24190_REG_ISC_EN_HIZ_MASK BIT(7)
13 #define BQ24190_REG_ISC_EN_HIZ_SHIFT 7
18 /* Power-On Configuration */
20 #define BQ24190_REG_POC_RESET_MASK BIT(7)
21 #define BQ24190_REG_POC_RESET_SHIFT 7
23 #define BQ24190_REG_POC_WDT_RESET_MASK BIT(6)
35 #define BQ24190_REG_POC_BOOST_LIM_MASK BIT(0)
40 #define BQ24190_REG_CCC_ICHG_MASK GENMASK(7, 2)
46 #define BQ24190_REG_CCC_FORCE_20PCT_MASK BIT(0)
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/Zephyr-latest/drivers/sensor/st/lsm9ds0_mfd/
Dlsm9ds0_mfd.h1 /* sensor_lsm9ds0_mfd.h - header file for LSM9DS0 accelerometer, magnetometer
8 * SPDX-License-Identifier: Apache-2.0
22 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMOR BIT(7)
23 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_ZYXMOR 7
24 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMOR BIT(6)
26 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMOR BIT(5)
28 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMOR BIT(4)
30 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMDA BIT(3)
32 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMDA BIT(2)
34 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMDA BIT(1)
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/Zephyr-latest/drivers/sensor/st/lsm6ds0/
Dlsm6ds0.h1 /* sensor_lsm6ds0.h - header file for LSM6DS0 accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
19 #define LSM6DS0_MASK_ACT_THS_SLEEP_ON_INACT_EN BIT(7)
20 #define LSM6DS0_SHIFT_ACT_THS_SLEEP_ON_INACT_EN 7
21 #define LSM6DS0_MASK_ACT_THS_ACT_THS (BIT(6) | BIT(5) | BIT(4) | \
22 BIT(3) | BIT(2) | BIT(1) | \
23 BIT(0))
29 #define LSM6DS0_MASK_INT_GEN_CFG_XL_AOI_XL BIT(7)
30 #define LSM6DS0_SHIFT_INT_GEN_CFG_XL_AOI_XL 7
31 #define LSM6DSO_MASK_INT_GEN_CFG_XL_6D BIT(6)
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/Zephyr-latest/drivers/sensor/st/lps22hb/
Dlps22hb.h1 /* sensor_lps25hb.h - header file for LPS22HB pressure and temperature
8 * SPDX-License-Identifier: Apache-2.0
22 #define LPS22HB_MASK_INTERRUPT_CFG_AUTORIFP BIT(7)
23 #define LPS22HB_SHIFT_INTERRUPT_CFG_AUTORIFP 7
24 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_ARP BIT(6)
26 #define LPS22HB_MASK_INTERRUPT_CFG_AUTOZERO BIT(5)
28 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_AZ BIT(4)
30 #define LPS22HB_MASK_INTERRUPT_CFG_DIFF_EN BIT(3)
32 #define LPS22HB_MASK_INTERRUPT_CFG_LIR BIT(2)
34 #define LPS22HB_MASK_INTERRUPT_CFG_PL_E BIT(1)
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/Zephyr-latest/drivers/gpio/
Dgpio_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
12 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
35 /* gpio port data register (bit mapping to pin) */
39 /* gpio port data mirror register (bit mapping to pin) */
41 /* gpio port output type register (bit mapping to pin) */
57 ((struct gpio_ite_data *)(dev)->data)
60 ((const struct gpio_ite_cfg *)(dev)->config)
63 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
73 * From WUESR1-WUESR4, the address increases by ones. From WUESR5 on in wuesr()
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/Zephyr-latest/drivers/sensor/apds9960/
Dapds9960.h5 * SPDX-License-Identifier: Apache-2.0
14 #define APDS9960_ENABLE_GEN BIT(6)
15 #define APDS9960_ENABLE_PIEN BIT(5)
16 #define APDS9960_ENABLE_AIEN BIT(4)
17 #define APDS9960_ENABLE_WEN BIT(3)
18 #define APDS9960_ENABLE_PEN BIT(2)
19 #define APDS9960_ENABLE_AEN BIT(1)
20 #define APDS9960_ENABLE_PON BIT(0)
32 #define APDS9960_PERS_PPERS (BIT(4) | BIT(5) | BIT(6) | BIT(7))
33 #define APDS9960_APERS_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
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/Zephyr-latest/drivers/sensor/ams/tmd2620/
Dtmd2620.h4 * SPDX-License-Identifier: Apache-2.0
15 #define TMD2620_ENABLE_WEN BIT(3)
16 #define TMD2620_ENABLE_PEN BIT(2)
17 #define TMD2620_ENABLE_PON BIT(0)
28 * If the WLONG bit is set:
57 #define TMD2620_PERS_PPERS (BIT(4) | BIT(5) | BIT(6) | BIT(7))
60 #define TMD2620_CFG0_WLONG BIT(2)
65 #define TMD2620_PCFG0_PPULSE_LEN_8US BIT(6)
66 #define TMD2620_PCFG0_PPULSE_LEN_16US BIT(7)
67 #define TMD2620_PCFG0_PPULSE_LEN_32US (BIT(6) | BIT(7))
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/Zephyr-latest/drivers/ieee802154/
Dieee802154_mcr20a_regs.h1 /* ieee802154_mcr20a_regs.h - Registers definition for NXP MCR20A */
6 * SPDX-License-Identifier: Apache-2.0
11 * which are used in the macros for the bit field manipulation.
47 #define MCR20A_REG_READ (BIT(7))
48 #define MCR20A_BUF_READ (BIT(7) | BIT(6))
49 #define MCR20A_BUF_BYTE_READ (BIT(7) | BIT(6) | BIT(5))
51 #define MCR20A_BUF_WRITE (BIT(6))
52 #define MCR20A_BUF_BYTE_WRITE (BIT(6) | BIT(5))
93 /* ---------------- (0x27) */
112 /* ---------------- (0x3a) */
[all …]
Dieee802154_cc2520_regs.h1 /* ieee802154_cc2520_regs.h - Registers definition for TI CC2520 */
6 * SPDX-License-Identifier: Apache-2.0
63 #define FRMFILT0_FRAME_FILTER_EN BIT(0)
64 #define FRMFILT0_PAN_COORDINATOR BIT(1)
68 #define FRMFILT1_ACCEPT_FT_0_BEACON BIT(3)
69 #define FRMFILT1_ACCEPT_FT_1_DATA BIT(4)
70 #define FRMFILT1_ACCEPT_FT_2_ACK BIT(5)
71 #define FRMFILT1_ACCEPT_FT_3_MAC_CMD BIT(6)
78 #define SRCMATCH_SRC_MATCH_EN BIT(0)
79 #define SRCMATCH_AUTOPEND BIT(1)
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/Zephyr-latest/drivers/ipm/
Dipm_nrfx_ipc.h4 * SPDX-License-Identifier: Apache-2.0
13 * Message channels are one-way connections between cores.
19 * SIGNAL0 -> CHANNEL0 -> EVENT0
24 * EVENT1 <- CHANNEL1 <- SIGNAL1
39 IPC_EVENT_BIT(7) | \
52 [0] = BIT(0),
53 [1] = BIT(1),
54 [2] = BIT(2),
55 [3] = BIT(3),
56 [4] = BIT(4),
[all …]
/Zephyr-latest/drivers/can/
Dcan_sja1000_priv.h4 * SPDX-License-Identifier: Apache-2.0
19 #define CAN_SJA1000_BTR1 (7U)
51 #define CAN_SJA1000_MOD_RM BIT(0)
52 #define CAN_SJA1000_MOD_LOM BIT(1)
53 #define CAN_SJA1000_MOD_STM BIT(2)
54 #define CAN_SJA1000_MOD_AFM BIT(3)
55 #define CAN_SJA1000_MOD_SM BIT(4)
58 #define CAN_SJA1000_CMR_TR BIT(0)
59 #define CAN_SJA1000_CMR_AT BIT(1)
60 #define CAN_SJA1000_CMR_RRB BIT(2)
[all …]
/Zephyr-latest/drivers/sensor/ams/tsl2540/
Dtsl2540.h2 * Copyright (c) 2022 T-Mobile USA, Inc.
4 * SPDX-License-Identifier: Apache-2.0
55 /* ENABLE(0x80: 0x00): Reserved:7:4 | WEN:3 | Reserved:2 | AEN:1 | PON:0 */
57 #define TSL2540_ENABLE_MASK (BIT(3) | BIT(1) | BIT(0))
58 #define TSL2540_ENABLE_CONF (BIT(3) | BIT(1) | BIT(0))
59 #define TSL2540_ENABLE_AEN_PON (BIT(1) | BIT(0))
62 /* CRG3(0xAB: 0x0C): INT_READ_CLEAR:7 | Reserved:6:5 | SAI:4 | Reserved:3:0 */
64 #define TSL2540_CFG3_MASK (BIT(7) | BIT(4))
65 #define TSL2540_CFG3_CONF (BIT(7) | BIT(4))
68 /* INTENAB(0xDD: 0x00): ASIEN:7 | Reserved:6:5 | AIEN:4 | Reserved:3:0 */
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/Zephyr-latest/drivers/sensor/st/lis2dh/
Dlis2dh.h4 * SPDX-License-Identifier: Apache-2.0
29 #define LIS2DH_AUTOINCREMENT_ADDR BIT(7)
32 #define LIS2DH_SDO_PU_DISC_MASK BIT(7)
35 #define LIS2DH_ACCEL_X_EN_BIT BIT(0)
36 #define LIS2DH_ACCEL_Y_EN_BIT BIT(1)
37 #define LIS2DH_ACCEL_Z_EN_BIT BIT(2)
43 #define LIS2DH_LP_EN_BIT_MASK BIT(3)
45 #define LIS2DH_LP_EN_BIT BIT(3)
58 #define LIS2DH_ODR_7 7
88 #define LIS2DH_HPIS1_EN_BIT BIT(0)
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/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v2.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
38 #define SSCR0_ECS BIT(6)
39 #define SSCR0_SSE BIT(7)
42 #define SSCR0_EDSS BIT(20)
43 #define SSCR0_NCS BIT(21)
44 #define SSCR0_RIM BIT(22)
45 #define SSCR0_TIM BIT(23)
46 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
48 #define SSCR0_ACS BIT(30)
[all …]
Dssp_regs_v1.h4 * SPDX-License-Identifier: Apache-2.0
30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
37 #define SSCR0_ECS BIT(6)
38 #define SSCR0_SSE BIT(7)
41 #define SSCR0_EDSS BIT(20)
42 #define SSCR0_NCS BIT(21)
43 #define SSCR0_RIM BIT(22)
44 #define SSCR0_TIM BIT(23)
45 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
47 #define SSCR0_ACS BIT(30)
[all …]
Dssp_regs_v3.h4 * SPDX-License-Identifier: Apache-2.0
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
45 #define SSCR0_RSVD1 BIT(6)
46 #define SSCR0_SSE BIT(7)
49 #define SSCR0_EDSS BIT(20)
50 #define SSCR0_RSVD2 BIT(21)
51 #define SSCR0_RIM BIT(22)
52 #define SSCR0_TIM BIT(23)
53 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
55 #define SSCR0_EFRDC BIT(27)
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/Zephyr-latest/drivers/sensor/bosch/bmi160/
Dbmi160.h5 * SPDX-License-Identifier: Apache-2.0
113 /* Indicates a read operation; bit 7 is clear on write s*/
114 #define BMI160_REG_READ BIT(7)
120 #define BMI160_ERR_FATAL BIT(0)
121 #define BMI160_ERR_CODE BIT(1)
123 #define BMI160_ERR_I2C_FAIL BIT(5)
124 #define BMI160_ERR_DROP_CMD BIT(6)
125 #define BMI160_ERR_MAG_DRDY BIT(7)
141 #define BMI160_STATUS_GYR_SELFTEST BIT(1)
142 #define BMI160_STATUS_MAG_MAN_OP BIT(2)
[all …]
/Zephyr-latest/drivers/sensor/ams/tsl2591/
Dtsl2591.h4 * SPDX-License-Identifier: Apache-2.0
18 /* Command: CMD:7 | TRANSACTION:6:5 | ADDR/SF:4:0 */
19 #define TSL2591_NORMAL_CMD (BIT(7) | BIT(5))
20 #define TSL2591_SPECIAL_CMD (BIT(7) | BIT(6) | BIT(5))
23 /* Enable: (0x00): NPIEN:7 | SAI:6 | Reserved:5 | AIEN:4 | Reserved:3:2 | AEN:1 | PON:0 */
24 #define TSL2591_POWER_MASK (BIT(1) | BIT(0))
25 #define TSL2591_POWER_ON (BIT(1) | BIT(0))
27 #define TSL2591_AEN_MASK (BIT(1))
28 #define TSL2591_AEN_ON (BIT(1))
30 #define TSL2591_AIEN_MASK (BIT(4))
[all …]
/Zephyr-latest/drivers/usb/uhc/
Duhc_max3421e.h4 * SPDX-License-Identifier: Apache-2.0
17 #define MAX3421E_CMD_DIR_WR BIT(1)
43 #define MAX3421E_REG_SNDBC 7U
48 #define MAX3421E_VBUSIRQ BIT(6)
49 #define MAX3421E_NOVBUSIRQ BIT(5)
50 #define MAX3421E_OSCOKIRQ BIT(0)
54 #define MAX3421E_VBUSIE BIT(6)
55 #define MAX3421E_NOVBUSIE BIT(5)
56 #define MAX3421E_OSCOKIE BIT(0)
60 #define MAX3421E_CHIPRES BIT(5)
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/Zephyr-latest/drivers/tee/optee/
Doptee_smc.h1 /* SPDX-License-Identifier: BSD-2-Clause */
3 * Copyright (c) 2015-2021, Linaro Limited
11 * This file is exported by OP-TEE and is in kept in sync between secure
70 * Normal cached memory (write-back), shareable for SMP systems and not
78 * 32-bit registers.
86 * 384fb3e0-e7f8-11e3-af63-0002a5d5c51b.
110 * Used by non-secure world to figure out which Trusted OS is installed.
113 * Returns UUID in a0-4 in the same way as OPTEE_SMC_CALLS_UID
123 * Used by non-secure world to figure out which version of the Trusted OS
127 * Returns revision in a0-1 in the same way as OPTEE_SMC_CALLS_REVISION
[all …]

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