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/Zephyr-Core-3.6.0/tests/unit/pot/
Dlog2.c29 zassert_equal(62, LOG2(BIT64(63) - 1)); in ZTEST()
30 zassert_equal(63, LOG2(BIT64(63))); in ZTEST()
31 zassert_equal(63, LOG2(BIT64(63) + 1)); in ZTEST()
32 zassert_equal(63, LOG2(UINT64_MAX)); in ZTEST()
Dlog2.cpp30 zassert_equal(62, LOG2(BIT64(63) - 1)); in ZTEST()
31 zassert_equal(63, LOG2(BIT64(63))); in ZTEST()
32 zassert_equal(63, LOG2(BIT64(63) + 1)); in ZTEST()
33 zassert_equal(63, LOG2(UINT64_MAX)); in ZTEST()
Dlog2ceil.c30 zassert_equal(63, LOG2CEIL(BIT64(63) - 1)); in ZTEST()
31 zassert_equal(63, LOG2CEIL(BIT64(63))); in ZTEST()
32 zassert_equal(64, LOG2CEIL(BIT64(63) + 1)); in ZTEST()
Dlog2ceil.cpp35 zassert_equal(63, LOG2CEIL(BIT64(63) - 1)); in ZTEST()
36 zassert_equal(63, LOG2CEIL(BIT64(63))); in ZTEST()
37 zassert_equal(64, LOG2CEIL(BIT64(63) + 1)); in ZTEST()
Dnhpot.c33 zassert_equal(BIT64(63), NHPOT(BIT64(63) - 1)); in ZTEST()
34 zassert_equal(BIT64(63), NHPOT(BIT64(63))); in ZTEST()
35 zassert_equal(0, NHPOT(BIT64(63) + 1)); in ZTEST()
Dnhpot.cpp36 zassert_equal(BIT64(63), NHPOT(BIT64(63) - 1)); in ZTEST()
37 zassert_equal(BIT64(63), NHPOT(BIT64(63))); in ZTEST()
38 zassert_equal(0, NHPOT(BIT64(63) + 1)); in ZTEST()
Dis_power_of_two.c24 zassert_true(IS_POWER_OF_TWO(BIT64(63))); in ZTEST()
25 zassert_false(IS_POWER_OF_TWO(BIT64(63) + 1)); in ZTEST()
/Zephyr-Core-3.6.0/drivers/dma/
Ddma_iproc_pax_v1.h72 uint64_t type : 4; /*type 63:60*/
81 uint64_t type : 2; /*type 63:62 set to b'11*/
88 uint64_t type : 2; /*63:62 set to b'11*/
93 uint64_t pcie_addr : 62; /*pcie_addr[63:2]*/
94 uint64_t type : 2; /*63:62 set to b'11*/
109 uint64_t type : 4;/*descriptor type 63:60*/
Ddma_iproc_pax_v2.h82 uint64_t type : 4; /*type:60:63*/
90 uint64_t type : 4; /*type:60:63*/
98 uint64_t type : 4; /*type:60:63*/
105 uint64_t type : 4;/*descriptor type 63:60*/
/Zephyr-Core-3.6.0/boards/arm/cy8cproto_063_ble/doc/
Dindex.rst10 enables design and debug of the Cypress PSoC 63 BLE MCU.
19 For more information about the PSoC 63 BLE MCU SoC and CY8CPROTO-063-BLE board:
21 - `PSoC 63 BLE MCU SoC Website`_
22 - `PSoC 63 BLE MCU Datasheet`_
23 - `PSoC 63 BLE MCU Architecture Reference Manual`_
24 - `PSoC 63 BLE MCU Register Reference Manual`_
68 The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for
123 .. _PSoC 63 BLE MCU SoC Website:
126 .. _PSoC 63 BLE MCU Datasheet:
129 .. _PSoC 63 BLE MCU Architecture Reference Manual:
[all …]
/Zephyr-Core-3.6.0/tests/lib/c_lib/common/src/
Dtest_qsort.c74 * NUMS="$(for i in `seq 0 63`; do echo -n "$(((RANDOM - 16384) % 100)), "; done)" in ZTEST()
80 15, -61, 36, -49, 24, -72, -63, 77, 88, -93, 13, 49, 41, in ZTEST()
81 35, -5, -72, -46, 64, -46, -97, -88, 90, 63, 49, 12, -58, in ZTEST()
88 -63, -61, -60, -58, -52, -52, -49, -46, -46, -42, -42, -35, -33, in ZTEST()
91 49, 52, 54, 61, 63, 64, 75, 77, 88, 90, 91, in ZTEST()
107 36, -49, 24, -72, -63, 77, 88, -93, 13, 49, 41, 35, -5, -72, in ZTEST()
108 -46, 64, -46, -97, 90, 63, 49, 12, -58, -76, 54, 75, 49, 11, in ZTEST()
117 -70, -69, -67, -63, -61, -60, -58, -57, -52, -52, -51, -49, -46, -46, in ZTEST()
121 41, 42, 42, 49, 49, 49, 51, 52, 54, 61, 63, 64, 74, 75, in ZTEST()
/Zephyr-Core-3.6.0/drivers/sensor/xmc4xxx_temp/
DKconfig18 The value is 7 bits in the range [-64, 63] which maps to -/+ 12.5C.
24 Gain adjustment of the temperature reading. Range [0, 63].
Dxmc4xxx_temp.c71 CONFIG_XMC4XXX_TEMP_CALIBRATE_OFFSET <= 63); in xmc4xxx_temp_init()
74 CONFIG_XMC4XXX_TEMP_CALIBRATE_OFFSET <= 63); in xmc4xxx_temp_init()
/Zephyr-Core-3.6.0/boards/arm/cy8ckit_062_ble/doc/
Dindex.rst10 enables design and debug of the Cypress PSoC 63 BLE MCU.
12 The PSoC 6 BLE Pioneer Kit features the PSoC 63 MCU: a dual-core MCU, with a
78 For more information about the PSoC 63 BLE MCU SoC and CY8CKIT-062-BLE board:
80 - `PSoC 63 BLE MCU SoC Website`_
81 - `PSoC 63 BLE MCU Datasheet`_
82 - `PSoC 63 BLE MCU Architecture Reference Manual`_
83 - `PSoC 63 BLE MCU Register Reference Manual`_
121 The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for
128 The PSoC 63 BLE MCU SoC has 8 SCB blocks and each one can be configured as
286 .. _PSoC 63 BLE MCU SoC Website:
[all …]
/Zephyr-Core-3.6.0/soc/arm/infineon_cat1/psoc6/
DKconfig.series25 bool "Infineon PSoC™ 63 series MCU (Connectivity Line)"
28 Enable support for Infineon PSoC™ 63 MCU series
/Zephyr-Core-3.6.0/subsys/net/
DKconfig.hostname30 range 1 63
31 default 63
/Zephyr-Core-3.6.0/dts/bindings/gpio/
Dxlnx,ps-gpio.yaml22 * Bank 3: EMIO pins [63:32] (total: 64 EMIO pins)
29 * Bank 4: EMIO pins [63:32]
/Zephyr-Core-3.6.0/soc/arm/st_stm32/stm32wb/
DKconfig.defconfig.stm32wb55xx12 default 63
/Zephyr-Core-3.6.0/samples/modules/tflite-micro/magic_wand/train/
Ddata_split_person_test.py37 dengyl_num = 63
38 liucx_num = 63
/Zephyr-Core-3.6.0/doc/security/media/
Dsensor-model.svg30 <rect x="307.5" y="208.996" width="146.5" height="63" fill="#c0c0ff"/>
37 <rect x="556" y="501" width="153" height="63" fill="#ffffc0"/>
38 …<rect x="556" y="501" width="153" height="63" stroke="gray" stroke-linecap="round" stroke-linejoin…
59 <rect x="266.5" y="452.5" width="153" height="63" fill="#ffffc0"/>
60 …<rect x="266.5" y="452.5" width="153" height="63" stroke="gray" stroke-linecap="round" stroke-line…
66 <rect x="549.5" y="319.5" width="153" height="63" fill="#ffffc0"/>
67 …<rect x="549.5" y="319.5" width="153" height="63" stroke="gray" stroke-linecap="round" stroke-line…
139 <rect x="103" y="274.612" width="146.5" height="63" fill="#c0c0ff"/>
146 <rect x="556" y="608.5135" width="146.5" height="63" fill="#c0c0ff"/>
/Zephyr-Core-3.6.0/dts/bindings/clock/
Dst,stm32f412-plli2s-clock.yaml26 Valid range: 2 - 63
/Zephyr-Core-3.6.0/boards/shields/ssd1306/
Dsh1106_128x64.overlay24 multiplex-ratio = <63>;
Dssd1306_128x64.overlay24 multiplex-ratio = <63>;
/Zephyr-Core-3.6.0/samples/modules/thrift/hello/
Dnative-key.pem7 KaiEFAc8T3T0n3PQcSRWoEdGCIy9TKjaFg6ovJqp755a8kgS8X9ukQdwRKbW/63F
/Zephyr-Core-3.6.0/dts/bindings/serial/
Dcypress,psoc6-uart.yaml31 For example the UART on PSoC-63 Pioneer Kit would be

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