| /Zephyr-Core-3.7.0/dts/arm/infineon/cat1b/cyw20829/ |
| D | cyw20829.dtsi | 42 interrupts = <7 6>, <6 6>;
49 interrupts = <0 6>;
51 ngpios = <6>;
58 interrupts = <1 6>;
67 interrupts = <2 6>;
69 ngpios = <6>;
76 interrupts = <3 6>;
85 interrupts = <4 6>;
94 interrupts = <5 6>;
111 interrupts = <8 6>;
[all …]
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| /Zephyr-Core-3.7.0/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/ |
| D | service_a_1.c | 44 '3', '3', '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6',
45 '6', '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8',
48 '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6', '6', '6',
49 '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8', '8', '9',
52 '4', '4', '4', '5', '5', '5', '5', '5', '6', '6', '6', '6', '6',
56 '4', '5', '5', '5', '5', '5', '6', '6', '6', '6', '6', '7', '7',
60 '5', '5', '5', '5', '6', '6', '6', '6', '6', '7', '7', '7', '7',
64 '5', '5', '6', '6', '6', '6', '6', '7', '7', '7', '7', '7', '8',
68 '6', '6', '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8',
71 '3', '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6', '6',
[all …]
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| /Zephyr-Core-3.7.0/dts/arm/nuvoton/npcx/npcx9/ |
| D | npcx9-miwus-wui-map.dtsi | 18 wui_cr_sin2: wui0-1-6-2 {
19 miwus = <&miwu0 0 6>; /* CR_SIN2 */
23 wui_io66: wui1-7-6 {
24 miwus = <&miwu1 6 6>; /* GPIO66 */
29 wui_i3c_sda: wui2-6-0 {
32 wui_iob6: wui2-6-6 {
33 miwus = <&miwu2 5 6>; /* GPIOB6 */
35 wui_lct: wui2-6-7 {
41 miwus = <&miwu2 6 4>; /* CR_SIN3 */
44 miwus = <&miwu2 6 5>; /* CR_SIN4 */
|
| /Zephyr-Core-3.7.0/dts/arm/infineon/cat1a/psoc6_01/ |
| D | psoc6_01.dtsi | 63 interrupts = <15 6>, <16 6>;
70 interrupts = <0 6>;
72 ngpios = <6>;
79 interrupts = <1 6>;
81 ngpios = <6>;
88 interrupts = <2 6>;
97 interrupts = <3 6>;
99 ngpios = <6>;
106 interrupts = <4 6>;
115 interrupts = <5 6>;
[all …]
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| /Zephyr-Core-3.7.0/dts/arm/infineon/cat1a/psoc6_02/ |
| D | psoc6_02.dtsi | 62 interrupts = <15 6>, <16 6>;
69 interrupts = <0 6>;
71 ngpios = <6>;
78 interrupts = <1 6>;
80 ngpios = <6>;
87 interrupts = <2 6>;
96 interrupts = <3 6>;
98 ngpios = <6>;
105 interrupts = <4 6>;
114 interrupts = <5 6>;
[all …]
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| /Zephyr-Core-3.7.0/dts/arm/nuvoton/npcx/npcx4/ |
| D | npcx4-miwus-wui-map.dtsi | 29 wui_io66: wui1-7-6 {
30 miwus = <&miwu1 6 6>; /* GPIO66 */
49 wui_io12: wui2-6-0 {
52 wui_smb2: wui2-6-3 {
55 wui_smb3: wui2-6-4 {
58 wui_iod6: wui2-6-5 {
61 wui_iob6: wui2-6-6 {
62 miwus = <&miwu2 5 6>; /* GPIOB6 */
64 wui_lct: wui2-6-7 {
70 miwus = <&miwu2 6 3>; /* CR_SIN2 */
[all …]
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| D | npcx4-lvol-ctrl-map.dtsi | 22 lvols = <&scfg 2 6>;
33 lvols = <&scfg 5 6>;
39 /* Low-Voltage IO Control 6 */
41 lvols = <&scfg 6 0>;
44 lvols = <&scfg 6 1>;
47 lvols = <&scfg 6 2>;
50 lvols = <&scfg 6 3>;
53 lvols = <&scfg 6 4>;
56 lvols = <&scfg 6 5>;
59 lvols = <&scfg 6 6>;
[all …]
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| /Zephyr-Core-3.7.0/include/zephyr/dt-bindings/pinctrl/renesas/ |
| D | pinctrl-r8a77951.h | 19 #define PIN_D6 RCAR_GP_PIN(0, 6)
35 #define PIN_A6 RCAR_GP_PIN(1, 6)
64 #define PIN_PWM0 RCAR_GP_PIN(2, 6)
79 #define PIN_SD1_CLK RCAR_GP_PIN(3, 6)
95 #define PIN_SD2_DS RCAR_GP_PIN(4, 6)
113 #define PIN_TX1_A RCAR_GP_PIN(5, 6)
133 #define PIN_SSI_SCK01239 RCAR_GP_PIN(6, 0)
134 #define PIN_SSI_WS01239 RCAR_GP_PIN(6, 1)
135 #define PIN_SSI_SDATA0 RCAR_GP_PIN(6, 2)
136 #define PIN_SSI_SDATA1_A RCAR_GP_PIN(6, 3)
[all …]
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| D | pinctrl-r8a77961.h | 20 #define PIN_D6 RCAR_GP_PIN(0, 6)
36 #define PIN_A6 RCAR_GP_PIN(1, 6)
65 #define PIN_PWM0 RCAR_GP_PIN(2, 6)
80 #define PIN_SD1_CLK RCAR_GP_PIN(3, 6)
96 #define PIN_SD2_DS RCAR_GP_PIN(4, 6)
114 #define PIN_TX1_A RCAR_GP_PIN(5, 6)
134 #define PIN_SSI_SCK01239 RCAR_GP_PIN(6, 0)
135 #define PIN_SSI_WS01239 RCAR_GP_PIN(6, 1)
136 #define PIN_SSI_SDATA0 RCAR_GP_PIN(6, 2)
137 #define PIN_SSI_SDATA1_A RCAR_GP_PIN(6, 3)
[all …]
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| /Zephyr-Core-3.7.0/dts/arm/nuvoton/npcx/ |
| D | npcx-miwus-wui-map.dtsi | 49 wui_mswc: wui0-2-6 {
50 miwus = <&miwu0 1 6>; /* MSWC */
75 wui_ioa4: wui0-3-6 {
76 miwus = <&miwu0 2 6>; /* GPIOA4 */
101 wui_iob2: wui0-4-6 {
102 miwus = <&miwu0 3 6>; /* GPIOB2 */
127 wui_host_acc: wui0-5-6 {
128 miwus = <&miwu0 4 6>; /* HOST_ACC */
135 wui_ioc0: wui0-6-0 {
138 wui_ioc1: wui0-6-1 {
[all …]
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| /Zephyr-Core-3.7.0/samples/shields/x_nucleo_53l0a1/src/ |
| D | display_7seg.h | 18 * 0| |6
25 #define CHAR_0 (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
26 #define CHAR_1 (BIT(5) | BIT(6))
28 #define CHAR_3 (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
29 #define CHAR_4 (BIT(1) | BIT(2) | BIT(5) | BIT(6))
30 #define CHAR_5 (BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(6))
31 #define CHAR_6 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(6))
32 #define CHAR_7 (BIT(3) | BIT(5) | BIT(6))
33 #define CHAR_8 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
34 #define CHAR_9 (BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
[all …]
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| /Zephyr-Core-3.7.0/dts/arm/infineon/cat1a/psoc6_04/ |
| D | psoc6_04.dtsi | 62 interrupts = <15 6>, <16 6>;
69 interrupts = <0 6>;
71 ngpios = <6>;
86 interrupts = <2 6>;
95 interrupts = <3 6>;
104 interrupts = <5 6>;
113 interrupts = <6 6>;
115 ngpios = <6>;
122 interrupts = <7 6>;
131 interrupts = <8 6>;
[all …]
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| /Zephyr-Core-3.7.0/include/zephyr/dt-bindings/pinctrl/ |
| D | ambiq-apollo4-pinctrl.h | 25 #define CT0_P0 APOLLO4_PINMUX(0, 6)
36 #define CT1_P1 APOLLO4_PINMUX(1, 6)
48 #define CT2_P2 APOLLO4_PINMUX(2, 6)
60 #define CT3_P3 APOLLO4_PINMUX(3, 6)
71 #define CT4_P4 APOLLO4_PINMUX(4, 6)
87 #define CT5_P5 APOLLO4_PINMUX(5, 6)
96 #define M0SDAWIR3_P6 APOLLO4_PINMUX(6, 0)
97 #define M0MOSI_P6 APOLLO4_PINMUX(6, 1)
98 #define I2S0_DATA_P6 APOLLO4_PINMUX(6, 2)
99 #define GPIO_P6 APOLLO4_PINMUX(6, 3)
[all …]
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| /Zephyr-Core-3.7.0/dts/arm/infineon/cat1a/psoc6_03/ |
| D | psoc6_03.dtsi | 62 interrupts = <15 6>, <16 6>;
69 interrupts = <0 6>;
71 ngpios = <6>;
78 interrupts = <2 6>;
87 interrupts = <3 6>;
96 interrupts = <5 6>;
105 interrupts = <6 6>;
114 interrupts = <7 6>;
123 interrupts = <8 6>;
132 interrupts = <9 6>;
[all …]
|
| /Zephyr-Core-3.7.0/boards/enjoydigital/litex_vexriscv/doc/img/ |
| D | symbiflow.svg | 1 …6-5 1.7-7.4 1.1-2.3 2.7-4.4 4.8-6.1 2.1-1.8 4.6-3.2 7.6-4.3 3-1.1 6.4-1.6 10.2-1.6 3.7 0 7 .5 9.9 …
|
| /Zephyr-Core-3.7.0/drivers/sensor/st/lsm9ds0_mfd/ |
| D | lsm9ds0_mfd.h | 24 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMOR BIT(6)
25 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_ZMOR 6
52 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_YMIEN BIT(6)
53 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_YMIEN 6
70 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_PTH_Y BIT(6)
71 #define LSM9DS0_MFD_SHIFT_INT_SRC_REG_M_M_PTH_Y 6
101 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_FIFO_EN BIT(6)
102 #define LSM9DS0_MFD_SHIFT_CTRL_REG0_XM_FIFO_EN 6
113 #define LSM9DS0_MFD_MASK_CTRL_REG1_XM_AODR (BIT(7) | BIT(6) | BIT(5) | \
126 #define LSM9DS0_MFD_MASK_CTRL_REG2_XM_ABW (BIT(7) | BIT(6))
[all …]
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| /Zephyr-Core-3.7.0/samples/tfm_integration/tfm_psa_test/ |
| D | README.rst | 71 [Check 1] Call get API for UID 6 which is not set
72 [Check 2] Call get_info API for UID 6 which is not set
73 [Check 3] Call remove API for UID 6 which is not set
74 [Check 4] Call get API for UID 6 which is removed
75 [Check 5] Call get_info API for UID 6 which is removed
76 [Check 6] Call remove API for UID 6 which is removed
77 Set storage for UID 6
83 [Check 1] Call get API for UID 6 which is not set
84 [Check 2] Call get_info API for UID 6 which is not set
85 [Check 3] Call remove API for UID 6 which is not set
[all …]
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| /Zephyr-Core-3.7.0/dts/arm/nuvoton/npcx/npcx7/ |
| D | npcx7-miwus-wui-map.dtsi | 18 wui_cr_sin2: wui0-1-6-2 {
19 miwus = <&miwu0 0 6>; /* CR_SIN2 */
23 wui_io86: wui0-1-6 {
24 miwus = <&miwu0 0 6>; /* GPIO86 */
28 wui_iod7: wui0-7-6 {
29 miwus = <&miwu0 6 6>; /* GPIOD7 */
|
| /Zephyr-Core-3.7.0/drivers/sensor/st/lsm9ds0_gyro/ |
| D | lsm9ds0_gyro.h | 23 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6))
24 #define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_DR 6
45 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I1_BOOT BIT(6)
46 #define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I1_BOOT 6
63 #define LSM9DS0_GYRO_MASK_CTRL_REG4_G_BLE BIT(6)
64 #define LSM9DS0_GYRO_SHIFT_CTRL_REG4_G_BLE 6
73 #define LSM9DS0_GYRO_MASK_CTRL_REG5_G_FIFO_EN BIT(6)
74 #define LSM9DS0_GYRO_SHIFT_CTRL_REG5_G_FIFO_EN 6
87 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_ZOR BIT(6)
88 #define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_ZOR 6
[all …]
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| /Zephyr-Core-3.7.0/samples/subsys/nvs/ |
| D | sample.yaml | 19 - "Id: 5, Longarray: 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b \
22 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 \
|
| /Zephyr-Core-3.7.0/boards/nxp/mimxrt1015_evk/ |
| D | mimxrt1015_evk-pinctrl.dtsi | 17 drive-strength = "r0-6";
27 drive-strength = "r0-6";
41 drive-strength = "r0-6";
51 drive-strength = "r0-6";
60 drive-strength = "r0-6";
68 drive-strength = "r0-6";
78 drive-strength = "r0-6";
87 drive-strength = "r0-6";
95 drive-strength = "r0-6";
108 drive-strength = "r0-6";
[all …]
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| /Zephyr-Core-3.7.0/drivers/pinctrl/renesas/rcar/ |
| D | pfc_r8a77951.c | 70 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
82 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
124 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
164 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
179 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
210 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
237 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
241 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
242 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
243 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
[all …]
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| D | pfc_r8a77961.c | 70 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
82 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
124 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
164 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
179 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
210 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
237 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
241 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
242 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
243 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
[all …]
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| /Zephyr-Core-3.7.0/drivers/sensor/st/lsm6dsl/ |
| D | lsm6dsl.h | 44 #define LSM6DSL_MASK_FIFO_CTRL1_FTH (BIT(7) | BIT(6) | \
53 #define LSM6DSL_MASK_FIFO_CTRL2_TIMER_PEDO_FIFO_DRDY BIT(6)
54 #define LSM6DSL_SHIFT_FIFO_CTRL2_TIMER_PEDO_FIFO_DRDY 6
72 #define LSM6DSL_MASK_FIFO_CTRL4_ONLY_HIGH_DATA BIT(6)
73 #define LSM6DSL_SHIFT_FIFO_CTRL4_ONLY_HIGH_DATA 6
82 #define LSM6DSL_MASK_FIFO_CTRL5_ODR_FIFO (BIT(6) | BIT(5) | \
98 #define LSM6DSL_MASK_INT1_CTRL_SIGN_MOT BIT(6)
99 #define LSM6DSL_SHIFT_INT1_CTRL_SIGN_MOT 6
116 #define LSM6DSL_MASK_INT2_CTRL_STEP_COUNT_OV BIT(6)
117 #define LSM6DSL_SHIFT_INT2_CTRL_STEP_COUNT_OV 6
[all …]
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| /Zephyr-Core-3.7.0/tests/net/traffic_class/ |
| D | testcase.yaml | 33 net.traffic_class.6:
35 - CONFIG_NET_TC_TX_COUNT=6
36 - CONFIG_NET_TC_RX_COUNT=6
62 net.traffic_class.6_no_rx:
64 - CONFIG_NET_TC_TX_COUNT=6
91 net.traffic_class.6_no_tx:
93 - CONFIG_NET_TC_RX_COUNT=6
123 - CONFIG_NET_TC_TX_COUNT=6
152 net.traffic_class.6_sr_ab:
155 - CONFIG_NET_TC_TX_COUNT=6
[all …]
|
