| /Zephyr-Core-3.5.0/boards/arm/mimxrt1040_evk/ |
| D | mimxrt1040_evk-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1042xjm5b-pinctrl.dtsi>
17 drive-strength = "r0-6";
18 slew-rate = "slow";
19 nxp,speed = "100-mhz";
23 /* Route PWM1 A3 to J16, pin 6 on arduino header */
27 drive-strength = "r0-6";
28 slew-rate = "fast";
29 nxp,speed = "100-mhz";
33 /* LPI2C1 SDA: J17 pin 9, LPI2C1 SCL: J17 pin 10 */
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| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | digilent,pmod.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 correspond to IO5 through IO8, as depicted below for a 12-pin connector.
11 12-pin Pmod interface:
15 2 IO3 IO7 6
17 - GND GND -
18 - VDD VDD -
20 This binding can also be used with the 6-pin Pmod connector variant which
21 is a proper subset of the 12-pin connector. In that case parent pins 4
25 6-pin Pmod interface:
31 - GND
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| D | quicklogic,eos-s3-gpio.yaml | 3 compatible: "quicklogic,eos-s3-gpio"
5 include: [gpio-controller.yaml, base.yaml]
11 "#gpio-cells":
14 pin-secondary-config:
19 a primary(0) or a secondary(1) pin. EOS S3 supports up to 8 GPIOs
22 "0 : 6 / 24"
28 "6 : 22 / 38"
30 E.g. configuring GPIO 2 as secondary results in controlling pin 28,
32 "pin-secondary-config = <0x04>;"
34 gpio-cells:
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| D | arduino-header-r3.yaml | 3 # SPDX-License-Identifier: Apache-2.0
11 Proceeding counter-clockwise:
12 * An 8-pin Power Supply header. No pins on this header are exposed
14 * A 6-pin Analog Input header. This has analog input signals
16 * An 8-pin header (opposite Analog Input). This has digital input
18 * A 10-pin header (opposite Power Supply). This has six additional
24 through 5 correspond to A0 through A5, and parent pins 6 through 21
29 AREF -
30 GND -
31 - N/C D13 19
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| D | atmel-xplained-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained layout provide a standard 10 pin header. A board can have
12 every pin can be defined as general purpose GPIO.
29 https://www.microchip.com/development-tools/xplained-boards
30 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
36 Bind Pin Name Pin Pin Pin Name Bind
39 4 SPI(CS0) 5 6 SPI(MOSI) 5
40 6 SPI(MISO) 7 8 SPI(SCK) 7
43 compatible: "atmel-xplained-header"
45 include: [gpio-nexus.yaml, base.yaml]
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| D | atmel-xplained-pro-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained Pro layout provide a standard 20 pin header. A board can have
9 names EXTn where n ϵ [1…7], n is determined by which ID pin is connected
28 https://www.microchip.com/development-tools/xplained-boards
29 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
35 Bind Pin Name Pin Pin Pin Name Bind
37 0 ADC(+) 3 4 ADC(-) 1
38 2 UART(RTS)/GPIO1 5 6 UART(CTS)/GPIO2 3
39 4 PWM(+) 7 8 PWM(-) 5
40 6 IRQ/GPIO3 9 10 SPI(CS1)/GPIO4 7
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| D | adafruit-feather-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 Proceeding counter-clockwise:
10 * A 16-pin header. 12 pins on this header are exposed
12 * A 12-pin header. 9 pins on this header are exposed
16 through 5 correspond to A0 through A5, and parent pins 6 through 20
19 - RESET
20 - 3V3
21 - 3V3
22 - GND
23 0 A0 - VBAT
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| D | particle-gen3-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 "shields" but use a different orientation and pin numbering scheme.
11 * A 12-pin header on the right. 9 pins on this header are exposed
13 * A 16-pin header. 13 pins on this header are exposed by this
17 0 through 8 correspond to the pins on the 12-pin header, starting
19 16-pin header, skipping the bottom pin then assigning 9 through 19,
20 skipping over GND, and replacing the lower 3V3 with pin 20. The
24 - 3V3
26 - GND
27 19 ADC0 LiPo+ -
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| /Zephyr-Core-3.5.0/dts/arm/cypress/ |
| D | psoc6.dtsi | 3 * Copyright (c) 2020-2021, ATL Electronics
5 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include "psoc6-pinctrl.dtsi"
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m0+";
25 compatible = "arm,cortex-m4f";
30 flash-controller@40250000 {
31 compatible = "cypress,psoc6-flash-controller";
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| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | nxp,s32ze-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The NXP S32 pin controller is a singleton node responsible for controlling
8 the pin function selection and pin properties. This node, labeled 'pinctrl' in
9 the SoC's devicetree, will define pin configurations in pin groups. Each group
10 within the pin configuration defines the pin configuration for a peripheral,
11 and each numbered subgroup in the pin group defines all the pins for that
20 #include <nxp/s32/S32Z27-BGA594-pinctrl.h>
26 output-enable;
30 input-enable;
35 The 'uart0_default' node contains the pin configurations for a particular state
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| D | ti,cc32xx-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 The TI CC32XX pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can
7 use this node to route UART0 RX to pin 55 and enable the pull-up resistor
8 on the pin.
17 All device pin configurations should be placed in child nodes of the
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
32 /* configure pin 55 as UART0 TX and pin 61 as UART0 CTS */
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| D | nxp,mcux-rt-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
15 drive-strength = "r0-6";
16 slew-rate = "slow";
17 nxp,speed = "100-mhz";
21 Both pins will be configured with a weak latch, drive strength of "r0-6",
26 input-schmitt-enable: HYS=1
27 drive-open-drain: ODE=1
28 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
29 bias-pull-down: PUE=1, PUS=<bias-pull-down-value>
30 bias-pull-up: PUE=1, PUS=<bias-pull-up-value>
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| /Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/reg/ |
| D | mec_gpio.h | 4 * SPDX-License-Identifier: Apache-2.0
13 #define MCHP_XEC_PINCTRL_REG_IDX(pin) ((pin >> 5) * 32 + (pin & 0x1f)) argument
19 volatile uint32_t PARIN[6];
21 volatile uint32_t PAROUT[6];
23 volatile uint32_t LOCK[6];
|
| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/ |
| D | esp-pinctrl-common.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/dt-util.h>
21 #define ESP32_PIN_SIGI_SHIFT 6U
26 #define ESP32_PINMUX(pin, sig_i, sig_o) \ argument
27 (((pin & ESP32_PIN_NUM_MASK) << ESP32_PIN_NUM_SHIFT) | \
32 * Definitions used to extract pin
34 * initial pin level
42 #define ESP32_PIN_EN_DIR_SHIFT 6U
50 /* Pin drive definitions */
55 * An output pin can be initialized
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| D | ti-cc32xx-pinctrl.h | 3 * SPDX-License-Identifier: Apache-2.0
10 * The whole TI CC32XX pin configuration information is encoded in a 32-bit
13 * - 31..22: Reserved
14 * - 21..16: Pin.
15 * - 15..10: Reserved.
16 * - 9: Pull-down flag.
17 * - 8: Pull-up flag.
18 * - 7..5: Drive strength.
19 * - 4: Enable open-drain flag.
20 * - 3..0: Configuration mode
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| D | stm32f1-pinctrl.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h>
11 #include <zephyr/dt-bindings/pinctrl/stm32f1-afio.h>
13 /* Adapted from Linux: include/dt-bindings/pinctrl/stm32-pinfunc.h */
16 * @brief Macro to generate pinmux int using port, pin number and mode arguments
17 * This is adapted from Linux equivalent st,stm32f429-pinctrl binding
24 #define STM32_PORT_SHIFT 6U
30 * @brief Pin configuration configuration bit field.
34 * - mode [ 0 : 1 ]
35 * - line [ 2 : 5 ]
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| /Zephyr-Core-3.5.0/dts/bindings/sensor/ |
| D | st,ism330dhcx-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: sensor-device.yaml
7 drdy-gpios:
8 type: phandle-array
10 DRDY gpio pin
12 This pin defaults to active high when produced by the sensor.
16 int-pin:
20 Select DRDY pin number (1 or 2).
29 configuration at power-up.
31 - 1
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| /Zephyr-Core-3.5.0/tests/drivers/gpio/gpio_basic_api/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
30 out_dev->name, in_dev->name); in board_setup()
37 * Configure pin mux. in board_setup()
43 printk("FATAL: input pin set in DTS %d != %d\n", PIN_IN, 15); in board_setup()
48 printk("FATAL: output pin set in DTS %d != %d\n", PIN_OUT, 14); in board_setup()
52 /* Configure pin RGMII2_RD2 as GPIO5_IO14. */ in board_setup()
60 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE(6); in board_setup()
62 /* Configure pin RGMII2_RD3 as GPIO5_IO15. */ in board_setup()
70 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE(6); in board_setup()
79 IOMUXC_SW_PAD_CTL_PAD_DSE(6)); in board_setup()
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| /Zephyr-Core-3.5.0/dts/bindings/net/wireless/ |
| D | nordic,nrf21540-fem.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 This is a representation of the nRF21540 Radio Front-End module.
8 See the "nordic,nrf21540-fem-spi" binding to configure the SPI
11 the FEM and SPI configurations using the spi-if property.
17 compatible = "nordic,nrf-spim";
19 cs-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
20 /* ... MISO/MOSI/SCK pin configuration goes here ... */
22 my_spi_if: nrf21540-spi@0 {
23 compatible = "nordic,nrf21540-fem-spi";
25 spi-max-frequency = <8000000>;
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| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | gpio_ite_it8xxx2.c | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
12 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
35 /* gpio port data register (bit mapping to pin) */
37 /* gpio port control register (byte mapping to pin) */
39 /* gpio port data mirror register (bit mapping to pin) */
41 /* gpio port output type register (bit mapping to pin) */
57 ((struct gpio_ite_data *)(dev)->data)
60 ((const struct gpio_ite_cfg *)(dev)->config)
63 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
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| /Zephyr-Core-3.5.0/tests/drivers/gpio/gpio_api_1pin/src/ |
| D | test_pin_interrupt.c | 4 * SPDX-License-Identifier: Apache-2.0
20 "Detected interrupt on an invalid pin"); in callback_edge()
31 "Detected interrupt on an invalid pin"); in callback_level()
37 "Failed to disable pin interrupt in the callback"); in callback_level()
41 static void pin_set_and_verify(const struct device *port, unsigned int pin, in pin_set_and_verify() argument
45 zassert_equal(gpio_pin_set(port, pin, val), 0, in pin_set_and_verify()
46 "Test point %d: failed to set logical pin value", idx); in pin_set_and_verify()
61 TC_PRINT("Running test on port=%s, pin=%d\n", port->name, TEST_PIN); in test_gpio_pin_interrupt_edge()
64 if (ret == -ENOTSUP) { in test_gpio_pin_interrupt_edge()
65 TC_PRINT("Simultaneous pin in/out mode is not supported.\n"); in test_gpio_pin_interrupt_edge()
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| /Zephyr-Core-3.5.0/soc/arm/cypress/common/ |
| D | soc_gpio.h | 2 * Copyright (c) 2016-2017 Piotr Mienkowski
4 * SPDX-License-Identifier: Apache-2.0
8 * @brief Cypress PSoC-6 MCU family General Purpose Input Output (GPIO)
19 * Pin flags/attributes
34 /* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */
37 /* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */
42 #define SOC_GPIO_IN_FILTER_POS (6)
69 uint32_t pinum; /** pin number */
70 uint32_t flags; /** pin flags/attributes */
74 * @brief Configure GPIO pin(s).
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| /Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/common/ |
| D | Kconfig.soc | 2 # SPDX-License-Identifier: Apache-2.0
16 bool "Support for external, SPI-connected RAM"
66 bool "ESP-PSRAM16 or APS1604"
69 bool "ESP-PSRAM32 or IS25WP032"
72 bool "ESP-PSRAM64 or LY68L6400"
124 menu "PSRAM clock and cs IO for ESP32-DOWD"
132 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
140 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
142 endmenu # PSRAM clock and cs IO for ESP32-DOWD
144 menu "PSRAM clock and cs IO for ESP32-D2WD"
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| /Zephyr-Core-3.5.0/tests/drivers/pinctrl/gd32/src/ |
| D | main_af.c | 3 * SPDX-License-Identifier: Apache-2.0
9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
19 zassert_equal(pcfg->state_cnt, 1U); in ZTEST()
21 scfg = &pcfg->states[0]; in ZTEST()
23 zassert_equal(scfg->id, PINCTRL_STATE_DEFAULT); in ZTEST()
24 zassert_equal(scfg->pin_cnt, 12U); in ZTEST()
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
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| D | main_afio.c | 3 * SPDX-License-Identifier: Apache-2.0
9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
19 zassert_equal(pcfg->state_cnt, 1U); in ZTEST()
21 scfg = &pcfg->states[0]; in ZTEST()
23 zassert_equal(scfg->id, PINCTRL_STATE_DEFAULT); in ZTEST()
24 zassert_equal(scfg->pin_cnt, 14U); in ZTEST()
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
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