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/Zephyr-Core-3.5.0/dts/bindings/pinctrl/
Dnxp,s32ze-pinctrl.yaml102 0: FMAX_3318 = 208 MHz (at 1.8 V), 166 MHz (at 3.3 V)
103 4: FMAX_3318 = 166 MHz (at 1.8 V), 150 MHz (at 3.3 V)
104 5: FMAX_3318 = 150 MHz (at 1.8 V), 133 MHz (at 3.3 V)
105 6: FMAX_3318 = 133 MHz (at 1.8 V), 100 MHz (at 3.3 V)
106 7: FMAX_3318 = 100 MHz (at 1.8 V), 83 MHz (at 3.3 V)
108 0: FMAX_18 = 208 MHz
109 4: FMAX_18 = 150 MHz
110 5: FMAX_18 = 133 MHz
111 6: FMAX_18 = 100 MHz
112 7: FMAX_18 = 50 MHz
[all …]
Dnxp,mcux-rt-pinctrl.yaml17 nxp,speed = "100-mhz";
22 slow slew rate, and 100 MHZ speed.
142 - "50-mhz"
143 - "100-mhz"
144 - "150-mhz"
145 - "200-mhz"
148 00 SPEED_0_low_50MHz_ — low(50MHz)
149 01 SPEED_1_medium_100MHz_ — medium(100MHz)
150 10 SPEED_2_medium_150MHz_ — medium(150MHz)
151 11 SPEED_3_max_200MHz_ — max(200MHz)
Dgd,gd32-pinctrl-afio.yaml75 signal (default: 2MHz). Only applies for ALTERNATE mode.
123 default: "max-speed-2mhz"
125 - "max-speed-10mhz"
126 - "max-speed-2mhz"
127 - "max-speed-50mhz"
131 slew rate of the output signal. Defaults to "max-speed-2mhz", the SoC
133 variants. If selected and not available the 50 MHz maximum speed will
Dnxp,imx8m-pinctrl.yaml93 110 45_OHM — 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
105 00 SLOW — Slow Frequency Slew Rate (50Mhz)
106 01 MEDIUM — Medium Frequency Slew Rate (100Mhz)
107 10 FAST — Fast Frequency Slew Rate (150Mhz)
108 11 MAX — Max Frequency Slew Rate (200Mhz)
Dgd,gd32-afio.yaml23 output speed is greater than 50MHz to reduce the I/O noise effects on
/Zephyr-Core-3.5.0/dts/bindings/clock/
Dnuvoton,npcx-pcc.yaml14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
35 120000000, 120 MHz
36 100000000, 100 MHz
37 96000000, 96 MHz
38 90000000, 90 MHz
39 80000000, 80 MHz
[all …]
Dst,stm32f4-pll-clock.yaml8 input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock
19 The PLL output frequency must not exceed 80 MHz.
45 Valid range: 50 - 432
/Zephyr-Core-3.5.0/boards/arm/mm_feather/
Dmm_feather-pinctrl.dtsi19 nxp,speed = "100-mhz";
31 nxp,speed = "100-mhz";
41 nxp,speed = "100-mhz";
52 nxp,speed = "100-mhz";
58 nxp,speed = "100-mhz";
69 nxp,speed = "100-mhz";
83 nxp,speed = "100-mhz";
92 nxp,speed = "100-mhz";
98 nxp,speed = "100-mhz";
102 /* fast pinmux settings for USDHC (over 100 Mhz) */
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/Zephyr-Core-3.5.0/boards/arm/mm_swiftio/
Dmm_swiftio-pinctrl.dtsi28 nxp,speed = "100-mhz";
39 nxp,speed = "100-mhz";
51 nxp,speed = "100-mhz";
61 nxp,speed = "100-mhz";
72 nxp,speed = "100-mhz";
78 nxp,speed = "100-mhz";
89 nxp,speed = "100-mhz";
103 nxp,speed = "100-mhz";
112 nxp,speed = "100-mhz";
118 nxp,speed = "100-mhz";
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/Zephyr-Core-3.5.0/boards/arm/mimxrt1020_evk/
Dmimxrt1020_evk-pinctrl.dtsi19 nxp,speed = "100-mhz";
30 nxp,speed = "50-mhz";
39 nxp,speed = "100-mhz";
54 nxp,speed = "200-mhz";
62 nxp,speed = "100-mhz";
68 nxp,speed = "100-mhz";
78 nxp,speed = "100-mhz";
90 nxp,speed = "100-mhz";
102 nxp,speed = "100-mhz";
116 nxp,speed = "100-mhz";
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/Zephyr-Core-3.5.0/boards/arm/mimxrt1024_evk/
Dmimxrt1024_evk-pinctrl.dtsi19 nxp,speed = "100-mhz";
30 nxp,speed = "50-mhz";
39 nxp,speed = "100-mhz";
54 nxp,speed = "200-mhz";
62 nxp,speed = "100-mhz";
68 nxp,speed = "100-mhz";
78 nxp,speed = "100-mhz";
90 nxp,speed = "100-mhz";
102 nxp,speed = "100-mhz";
116 nxp,speed = "100-mhz";
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/Zephyr-Core-3.5.0/boards/arm/cy8cproto_063_ble/
Dcy8cproto_063_ble.dts102 /* CM4 core clock = 100MHz
103 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
109 /* CM0+ core clock = 50MHz
110 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
116 /* PERI core clock = 100MHz
117 * &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz
/Zephyr-Core-3.5.0/boards/arm/mimxrt1064_evk/
Dmimxrt1064_evk-pinctrl.dtsi20 nxp,speed = "100-mhz";
32 nxp,speed = "100-mhz";
49 nxp,speed = "100-mhz";
60 nxp,speed = "50-mhz";
70 nxp,speed = "100-mhz";
86 nxp,speed = "200-mhz";
97 nxp,speed = "100-mhz";
107 nxp,speed = "100-mhz";
117 nxp,speed = "100-mhz";
129 nxp,speed = "100-mhz";
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/Zephyr-Core-3.5.0/boards/arm/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6-pinctrl.dtsi19 nxp,speed = "100-mhz";
28 nxp,speed = "50-mhz";
43 nxp,speed = "200-mhz";
50 nxp,speed = "200-mhz";
58 nxp,speed = "50-mhz";
68 nxp,speed = "100-mhz";
78 nxp,speed = "100-mhz";
88 nxp,speed = "100-mhz";
99 nxp,speed = "200-mhz";
109 nxp,speed = "200-mhz";
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/Zephyr-Core-3.5.0/boards/arm/cy8cproto_062_4343w/
Dcy8cproto_062_4343w.dts82 /* CM4 core clock = 100MHz
83 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
89 /* CM0+ core clock = 50MHz
90 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
96 /* PERI core clock = 100MHz
97 * &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz
/Zephyr-Core-3.5.0/boards/arm/mimxrt1060_evk/
Dmimxrt1060_evk-pinctrl.dtsi20 nxp,speed = "100-mhz";
32 nxp,speed = "100-mhz";
49 nxp,speed = "100-mhz";
60 nxp,speed = "50-mhz";
70 nxp,speed = "100-mhz";
86 nxp,speed = "200-mhz";
96 nxp,speed = "100-mhz";
108 nxp,speed = "100-mhz";
120 nxp,speed = "100-mhz";
131 nxp,speed = "100-mhz";
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/Zephyr-Core-3.5.0/boards/arm/mimxrt1050_evk/
Dmimxrt1050_evk-pinctrl.dtsi20 nxp,speed = "100-mhz";
32 nxp,speed = "100-mhz";
49 nxp,speed = "100-mhz";
60 nxp,speed = "50-mhz";
70 nxp,speed = "100-mhz";
86 nxp,speed = "200-mhz";
97 nxp,speed = "100-mhz";
107 nxp,speed = "100-mhz";
119 nxp,speed = "100-mhz";
131 nxp,speed = "200-mhz";
[all …]
/Zephyr-Core-3.5.0/include/zephyr/drivers/pinctrl/
Dpinctrl_soc_gd32_common.h107 /** Maximum 2MHz */
112 /** Maximum 10MHz */
114 /** Maximum 50MHz */
117 /** Maximum 25MHz */
119 /** Maximum 50MHz */
126 /** Maximum 10MHz */
128 /** Maximum 2MHz */
130 /** Maximum 50MHz */
/Zephyr-Core-3.5.0/drivers/ieee802154/
DKconfig.cc120087 bool "IEEE 802.15.4g SUN MR-FSK, 863MHz band, mode #1 - channel page 9, 34 channels, 50Kbps (ETSI)"
93 bool "IEEE 802.15.4g SUN MR-FSK 920MHz band, mode #1 - channel page 9, 39 channels, 50Kbps (ARIB)"
99 bool "IEEE 802.15.4 Non-Standard 2-GFSK 433MHz band - channel page 9, 15 channels, 50Kbps (ETSI)"
/Zephyr-Core-3.5.0/soc/arc/snps_arc_iot/
Dsysconf.c11 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(16)
30 /* the following configuration is based on Fin = 16 Mhz */
32 {100, PLL_CONF_VAL(1, 25, 2)}, /* 100 Mhz */
33 {50, PLL_CONF_VAL(1, 25, 3)}, /* 50 Mhz */
34 {150, PLL_CONF_VAL(4, 75, 1)}, /* 150 Mhz */
35 {75, PLL_CONF_VAL(4, 75, 2)}, /* 75 Mhz */
36 {25, PLL_CONF_VAL(2, 25, 3)}, /* 25 Mhz */
37 {72, PLL_CONF_VAL(8, 144, 2)}, /* 72 Mhz */
38 {144, PLL_CONF_VAL(8, 144, 1)}, /* 144 Mhz */
51 * 1 Mhz <= Fref <= 50 Mhz
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/Zephyr-Core-3.5.0/soc/arm/nuvoton_npcx/
DKconfig56 bool "SPI flash max clock rate of 20 MHz"
59 bool "SPI flash max clock rate of 25 MHz"
62 bool "SPI flash max clock rate of 33 MHz"
66 bool "SPI flash max clock rate of 40 MHz"
69 bool "SPI flash max clock rate of 50 MHz"
78 default 50 if NPCX_HEADER_SPI_MAX_CLOCK_50
/Zephyr-Core-3.5.0/tests/drivers/pinctrl/gd32/boards/
Dgd32f450i_eval.overlay45 slew-rate = "max-speed-2mhz";
49 slew-rate = "max-speed-25mhz";
53 slew-rate = "max-speed-50mhz";
57 slew-rate = "max-speed-200mhz";
/Zephyr-Core-3.5.0/boards/arm/mimxrt1040_evk/
Dmimxrt1040_evk-pinctrl.dtsi19 nxp,speed = "100-mhz";
29 nxp,speed = "100-mhz";
41 nxp,speed = "100-mhz";
53 nxp,speed = "100-mhz";
66 nxp,speed = "100-mhz";
76 nxp,speed = "100-mhz";
87 nxp,speed = "50-mhz";
93 nxp,speed = "100-mhz";
/Zephyr-Core-3.5.0/boards/arm/teensy4/
Dteensy4-pinctrl.dtsi22 nxp,speed = "200-mhz";
30 nxp,speed = "200-mhz";
42 nxp,speed = "100-mhz";
48 nxp,speed = "100-mhz";
60 nxp,speed = "100-mhz";
72 nxp,speed = "100-mhz";
84 nxp,speed = "100-mhz";
97 nxp,speed = "100-mhz";
110 nxp,speed = "100-mhz";
123 nxp,speed = "100-mhz";
[all …]
/Zephyr-Core-3.5.0/soc/arm/atmel_sam0/common/
Dsoc_saml2x.c22 * the CPU clock will be configured to 48 MHz, and run via DFLL48M.
26 * GCLK Gen 0 -> GCLK_MAIN @ 48 Mhz
28 * GCLK Gen 2 -> USB @ 48 MHz
29 * GCLK Gen 3 -> ADC @ 24 MHz (further /2 in the ADC peripheral)
38 /* by default, OSC16M will be enabled at 4 MHz, and the CPU will in gclk_reset()
144 /* if the target frequency is 48 MHz, then the calibration value can be used to in dfll48m_init()
163 | OSCCTRL_DFLLVAL_FINE(512) /* use 50% */ in dfll48m_init()
169 * example values for these - I have seen others using ~50%. hopefully these in dfll48m_init()
178 /* use a 16 MHz -> 31.25 kHz reference... 48e6 / 31,250 = 1,536 in dfll48m_init()
180 * 16 MHz source directly in dfll48m_init()
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