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/Zephyr-Core-3.6.0/tests/net/lib/lwm2m/content_senml_cbor/src/
Dmain.c22 #define TEST_RES_FLOAT 5
184 (0x04 << 5) | 1, in ZTEST()
185 (0x05 << 5) | 3, in ZTEST()
186 (0x01 << 5) | 1, in ZTEST()
187 (0x03 << 5) | 9, in ZTEST()
188 '/', '6', '5', '5', '3', '5', '/', '0', '/', in ZTEST()
189 (0x00 << 5) | 0, in ZTEST()
190 (0x03 << 5) | 1, in ZTEST()
192 (0x00 << 5) | 2, in ZTEST()
193 (0x00 << 5) | 0 in ZTEST()
[all …]
/Zephyr-Core-3.6.0/samples/subsys/zbus/priority_boost/
Dsample.yaml10 - "I: 0 -> T1: prio before 5"
11 - "I: 0 ---> L1: T1 prio 5"
12 - "I: 0 ---> L2: T1 prio 5"
13 - "I: 0 -> T1: prio after 5"
14 - "I: 1 -> T1: prio before 5"
15 - "I: 1 ---> L1: T1 prio 5"
16 - "I: 1 ---> L2: T1 prio 5"
17 - "I: 1 -> T1: prio after 5"
18 - "I: 2 -> T1: prio before 5"
19 - "I: 2 ---> L1: T1 prio 5"
[all …]
DREADME.rst61 I: 0 -> T1: prio before 5
62 I: 0 ---> L1: T1 prio 5
63 I: 0 -> MS1: T1 prio 5
64 I: 0 -> MS2: T1 prio 5
65 I: 0 ---> L2: T1 prio 5
66 I: 0 -> T1: prio after 5
67 I: N -> S1: T1 prio 5
68 I: 0 -> S1: T1 prio 5
70 I: 1 -> T1: prio before 5
71 I: 1 ---> L1: T1 prio 5
[all …]
Dzbus_publishing_process_example_scenario.svg2 <rect y="77" width="330" height="128" rx="5" fill="#6931D0"/>
3 <path d="M31.188 157.5V154.08L39.036 132.012H31.62V128.34H44.4V131.076L36.264 153.828H44.436V157.5H…
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11 <path d="M182 231L190.66 216L173.34 216L182 231ZM180.5 173L180.5 217.5L183.5 217.5L183.5 173L180.5 …
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16 <path d="M358 163L343 154.34L343 171.66L358 163ZM300 164.5L344.5 164.5L344.5 161.5L300 161.5L300 16…
[all …]
/Zephyr-Core-3.6.0/samples/kernel/condition_variables/simple/
DREADME.rst38 [thread 0] working (0/5)
39 [thread 1] working (0/5)
40 [thread 2] working (0/5)
41 [thread 3] working (0/5)
42 [thread 4] working (0/5)
43 [thread 5] working (0/5)
44 [thread 6] working (0/5)
45 [thread 7] working (0/5)
46 [thread 8] working (0/5)
47 [thread 9] working (0/5)
[all …]
/Zephyr-Core-3.6.0/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/
Dservice_a_1.c44 '3', '3', '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6',
48 '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6', '6', '6',
52 '4', '4', '4', '5', '5', '5', '5', '5', '6', '6', '6', '6', '6',
56 '4', '5', '5', '5', '5', '5', '6', '6', '6', '6', '6', '7', '7',
59 '2', '2', '3', '3', '3', '3', '3', '4', '4', '4', '4', '4', '5',
60 '5', '5', '5', '5', '6', '6', '6', '6', '6', '7', '7', '7', '7',
63 '3', '3', '3', '3', '3', '4', '4', '4', '4', '4', '5', '5', '5',
64 '5', '5', '6', '6', '6', '6', '6', '7', '7', '7', '7', '7', '8',
67 '3', '3', '3', '4', '4', '4', '4', '4', '5', '5', '5', '5', '5',
71 '3', '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6', '6',
[all …]
/Zephyr-Core-3.6.0/tests/ztest/zexpect/src/
Dmain.c19 uint32_t val = 5; in ZTEST()
22 zexpect_not_equal(val, 5); in ZTEST()
59 zexpect_ok(5); in ZTEST()
103 zexpect_equal(5, 5); in ZTEST()
109 zexpect_equal(5, 1); in ZTEST()
114 zexpect_not_equal(5, 1); in ZTEST()
120 zexpect_not_equal(5, 5); in ZTEST()
144 zexpect_within(7, 5, 2); in ZTEST()
153 zexpect_within(7, 5, 1); in ZTEST()
158 zexpect_between_inclusive(-5, -10, 0); in ZTEST()
[all …]
/Zephyr-Core-3.6.0/dts/arm/nuvoton/npcx/
Dnpcx-miwus-wui-map.dtsi46 wui_io95: wui0-2-5 {
47 miwus = <&miwu0 1 5>; /* GPIO95 */
72 wui_ioa3: wui0-3-5 {
73 miwus = <&miwu0 2 5>; /* GPIOA3 */
98 wui_iob1: wui0-4-5 {
99 miwus = <&miwu0 3 5>; /* GPIOB1 */
109 wui_iob3: wui0-5-0 {
112 wui_iob4: wui0-5-1 {
115 wui_iob5: wui0-5-2 {
118 wui_smb4: wui0-5-3 {
[all …]
/Zephyr-Core-3.6.0/drivers/sensor/lsm9ds0_mfd/
Dlsm9ds0_mfd.h26 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMOR BIT(5)
27 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_YMOR 5
54 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_ZMIEN BIT(5)
55 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_ZMIEN 5
72 #define LSM9DS0_MFD_MASK_INT_SRC_REG_M_M_PTH_Z BIT(5)
73 #define LSM9DS0_MFD_SHIFT_INT_SRC_REG_M_M_PTH_Z 5
103 #define LSM9DS0_MFD_MASK_CTRL_REG0_XM_WTM_EN BIT(5)
104 #define LSM9DS0_MFD_SHIFT_CTRL_REG0_XM_WTM_EN 5
113 #define LSM9DS0_MFD_MASK_CTRL_REG1_XM_AODR (BIT(7) | BIT(6) | BIT(5) | \
128 #define LSM9DS0_MFD_MASK_CTRL_REG2_XM_AFS (BIT(5) | BIT(4) | BIT(3))
[all …]
/Zephyr-Core-3.6.0/drivers/sensor/bme280/
Dbme280.h84 #define BME280_TEMP_OVER (1 << 5)
86 #define BME280_TEMP_OVER (2 << 5)
88 #define BME280_TEMP_OVER (3 << 5)
90 #define BME280_TEMP_OVER (4 << 5)
92 #define BME280_TEMP_OVER (5 << 5)
104 #define BME280_PRESS_OVER (5 << 2)
116 #define BME280_HUMIDITY_OVER 5
122 #define BME280_STANDBY (1 << 5)
124 #define BME280_STANDBY (2 << 5)
126 #define BME280_STANDBY (3 << 5)
[all …]
/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a77951.h18 #define PIN_D5 RCAR_GP_PIN(0, 5)
34 #define PIN_A5 RCAR_GP_PIN(1, 5)
63 #define PIN_IRQ5 RCAR_GP_PIN(2, 5)
78 #define PIN_SD0_DATA3 RCAR_GP_PIN(3, 5)
94 #define PIN_SD2_DATA3 RCAR_GP_PIN(4, 5)
107 #define PIN_SCK0 RCAR_GP_PIN(5, 0)
108 #define PIN_RX0 RCAR_GP_PIN(5, 1)
109 #define PIN_TX0 RCAR_GP_PIN(5, 2)
110 #define PIN_CTS0 RCAR_GP_PIN(5, 3)
111 #define PIN_RTS0 RCAR_GP_PIN(5, 4)
[all …]
/Zephyr-Core-3.6.0/samples/subsys/nvs/
Dsample.yaml19 - "Id: 5, Longarray: 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b \
22 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 \
/Zephyr-Core-3.6.0/soc/arm64/renesas_rcar/gen3/
Dpfc_r8a77961.c19 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
37 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
60 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
61 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
62 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
63 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
67 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
68 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
69 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
70 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
[all …]
/Zephyr-Core-3.6.0/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-miwus-wui-map.dtsi35 wui_slp_msc: wui2-5-0 {
38 wui_z8: wui2-5-1 {
41 wui_z9: wui2-5-2 {
44 wui_z10: wui2-5-3 {
50 miwus = <&miwu2 5 0>; /* GPIO12 */
53 miwus = <&miwu2 5 3>; /* SMB2 */
56 miwus = <&miwu2 5 4>; /* SMB3 */
58 wui_iod6: wui2-6-5 {
59 miwus = <&miwu2 5 5>; /* GPIOD6 */
62 miwus = <&miwu2 5 6>; /* GPIOB6 */
[all …]
/Zephyr-Core-3.6.0/tests/net/traffic_class/
Dtestcase.yaml29 net.traffic_class.5:
31 - CONFIG_NET_TC_TX_COUNT=5
32 - CONFIG_NET_TC_RX_COUNT=5
58 net.traffic_class.5_no_rx:
60 - CONFIG_NET_TC_TX_COUNT=5
87 net.traffic_class.5_no_tx:
89 - CONFIG_NET_TC_RX_COUNT=5
118 - CONFIG_NET_TC_RX_COUNT=5
126 - CONFIG_NET_TC_RX_COUNT=5
147 net.traffic_class.5_sr_ab:
[all …]
/Zephyr-Core-3.6.0/drivers/sensor/lsm6dsl/
Dlsm6dsl.h31 #define LSM6DSL_MASK_FUNC_CFG_EN_B BIT(5)
32 #define LSM6DSL_SHIFT_FUNC_CFG_EN_B 5
45 BIT(5) | BIT(4) | \
62 #define LSM6DSL_MASK_FIFO_CTRL3_DEC_FIFO_GYRO (BIT(5) | BIT(4) | \
74 #define LSM6DSL_MASK_FIFO_CTRL4_DEC_DS4_FIFO (BIT(5) | BIT(4) | \
82 #define LSM6DSL_MASK_FIFO_CTRL5_ODR_FIFO (BIT(6) | BIT(5) | \
100 #define LSM6DSL_MASK_INT1_CTRL_FULL_FLAG BIT(5)
101 #define LSM6DSL_SHIFT_INT1_CTRL_FULL_FLAG 5
118 #define LSM6DSL_MASK_INT2_CTRL_FULL_FLAG BIT(5)
119 #define LSM6DSL_SHIFT_INT2_CTRL_FULL_FLAG 5
[all …]
/Zephyr-Core-3.6.0/drivers/sensor/lsm6ds0/
Dlsm6ds0.h21 #define LSM6DS0_MASK_ACT_THS_ACT_THS (BIT(6) | BIT(5) | BIT(4) | \
33 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZHIE_XL BIT(5)
34 #define LSM6DS0_SHIFT_INT_GEN_CFG_XL_ZHIE_XL 5
57 #define LSM6DS0_MASK_INT_CTRL_INT_FSS5 BIT(5)
58 #define LSM6DS0_SHIFT_INT_CTRL_INT_FSS5 5
74 #define LSM6DS0_MASK_CTRL_REG1_G_ODR_G (BIT(7) | BIT(6) | BIT(5))
75 #define LSM6DS0_SHIFT_CTRL_REG1_G_ODR_G 5
97 #define LSM6DS0_MASK_ORIENT_CFG_G_SIGNX_G BIT(5)
98 #define LSM6DS0_SHIFT_ORIENT_CFG_G_SIGNX_G 5
109 #define LSM6DS0_MASK_INT_GEN_SRC_G_ZH_G BIT(5)
[all …]
/Zephyr-Core-3.6.0/dts/bindings/clock/
Dnuvoton,npcx-pcc.yaml15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
65 5, CORE_CLK = OFMCLK / 5
76 - 5
96 5, APB1_CLK = OFMCLK / 5
107 - 5
127 5, APB2_CLK = OFMCLK / 5
138 - 5
[all …]
/Zephyr-Core-3.6.0/doc/services/zbus/images/
Dzbus_publishing_process_example_scenario.svg2 <rect y="77" width="330" height="128" rx="5" fill="#6931D0"/>
3 <path d="M31.188 157.5V154.08L39.036 132.012H31.62V128.34H44.4V131.076L36.264 153.828H44.436V157.5H…
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6 <path d="M281 231L289.66 216L272.34 216L281 231ZM279.5 173L279.5 217.5L282.5 217.5L282.5 173L279.5 …
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11 <path d="M182 231L190.66 216L173.34 216L182 231ZM180.5 173L180.5 217.5L183.5 217.5L183.5 173L180.5 …
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16 <path d="M358 163L343 154.34L343 171.66L358 163ZM300 164.5L344.5 164.5L344.5 161.5L300 161.5L300 16…
[all …]
/Zephyr-Core-3.6.0/drivers/sensor/lps22hb/
Dlps22hb.h26 #define LPS22HB_MASK_INTERRUPT_CFG_AUTOZERO BIT(5)
27 #define LPS22HB_SHIFT_INTERRUPT_CFG_AUTOZERO 5
43 #define LPS22HB_MASK_CTRL_REG1_ODR (BIT(6) | BIT(5) | BIT(4))
59 #define LPS22HB_MASK_CTRL_REG2_STOP_ON_FTH BIT(5)
60 #define LPS22HB_SHIFT_CTRL_REG2_STOP_ON_FTH 5
75 #define LPS22HB_MASK_CTRL_REG3_F_FSS5 BIT(5)
76 #define LPS22HB_SHIFT_CTRL_REG3_F_FFS5 5
87 #define LPS22HB_MASK_FIFO_CTRL_F_MODE (BIT(7) | BIT(6) | BIT(5))
88 #define LPS22HB_SHIFT_FIFO_CTRL_F_MODE 5
117 #define LPS22HB_MASK_FIFO_STATUS_EMPTY_FIFO BIT(5)
[all …]
/Zephyr-Core-3.6.0/dts/arm/infineon/
Dxmc4500_F100x1024-intc.dtsi11 XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */
16 XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */
23 XMC4XXX_INTC_SET_LINE_MAP(1, 5, 0, 2) /* ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 */
26 XMC4XXX_INTC_SET_LINE_MAP(0, 7, 5, 2) /* ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 */
34 XMC4XXX_INTC_SET_LINE_MAP(3, 5, 5, 3) /* ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 */
35 XMC4XXX_INTC_SET_LINE_MAP(1, 5, 0, 4) /* ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 */
37 XMC4XXX_INTC_SET_LINE_MAP(1, 15, 0, 5) /* ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 */
38 XMC4XXX_INTC_SET_LINE_MAP(2, 7, 4, 5) /* ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 */
41 XMC4XXX_INTC_SET_LINE_MAP(0, 5, 0, 7) /* ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 */
/Zephyr-Core-3.6.0/drivers/sensor/lsm9ds0_gyro/
Dlsm9ds0_gyro.h25 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_BW (BIT(5) | BIT(4))
37 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPM (BIT(5) | BIT(4))
47 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_H_L BIT(5)
48 #define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_H_L 5
65 #define LSM9DS0_GYRO_MASK_CTRL_REG4_G_FS (BIT(5) | BIT(4))
89 #define LSM9DS0_GYRO_MASK_STATUS_REG_G_YOR BIT(5)
90 #define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_YOR 5
110 #define LSM9DS0_GYRO_MASK_FIFO_CTRL_REG_G_FM (BIT(7) | BIT(6) | BIT(5))
111 #define LSM9DS0_GYRO_SHIFT_FIFO_CTRL_REG_G_FM 5
121 #define LSM9DS0_GYRO_MASK_FIFO_SRC_REG_G_EMPTY BIT(5)
[all …]
/Zephyr-Core-3.6.0/drivers/ieee802154/
Dieee802154_rf2xx_regs.h19 #define RX2XX_FRAME_MIN_PHR_SIZE 5
101 #define RF2XX_TRAC_STATUS 5
117 #define RF2XX_TX_AUTO_CRC_ON 5
126 #define RF2XX_GC_PA 5
132 #define RF2XX_RND_VALUE 5
138 #define RF2XX_CCA_MODE 5
147 #define RF2XX_JCM_EN 5
153 #define RF2XX_OQPSK_SCRAM_EN 5
175 #define RF2XX_AMI 5
190 #define RF2XX_BATMON_OK 5
[all …]
/Zephyr-Core-3.6.0/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/src/mesh/
Dpublisher.c71 bt_mesh_model_msg_init(root_models[5].pub->msg, in publish()
73 net_buf_simple_add_le16(root_models[5].pub->msg, LEVEL_S25); in publish()
74 net_buf_simple_add_u8(root_models[5].pub->msg, tid++); in publish()
75 err = bt_mesh_model_publish(&root_models[5]); in publish()
81 bt_mesh_model_msg_init(root_models[5].pub->msg, in publish()
83 net_buf_simple_add_le32(root_models[5].pub->msg, 100); in publish()
84 net_buf_simple_add_u8(root_models[5].pub->msg, tid++); in publish()
85 err = bt_mesh_model_publish(&root_models[5]); in publish()
87 bt_mesh_model_msg_init(root_models[5].pub->msg, in publish()
89 net_buf_simple_add_le16(root_models[5].pub->msg, 655); in publish()
[all …]
/Zephyr-Core-3.6.0/dts/bindings/interrupt-controller/
Dst,stm32-exti.yaml32 <4 1>, <5 5>, <10 6>;
34 5 first lines contain one element
35 6th line starts with input line 5 and contains 5 elements (5 to 9)

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