Searched +full:40 +full:mhz (Results 1 – 25 of 93) sorted by relevance
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| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | nxp,imx8m-pinctrl.yaml | 15 drive-strength = "40-ohm";
81 - "40-ohm"
93 110 45_OHM — 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
94 111 40_OHM — 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
105 00 SLOW — Slow Frequency Slew Rate (50Mhz)
106 01 MEDIUM — Medium Frequency Slew Rate (100Mhz)
107 10 FAST — Fast Frequency Slew Rate (150Mhz)
108 11 MAX — Max Frequency Slew Rate (200Mhz)
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/ethernet/ |
| D | xlnx_gem.h | 28 #define XLNX_GEM_MDC_DIVIDER_8 0 /* cpu_1x or IOU_SWITCH_CLK < 20 MHz */
29 #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */
30 #define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or IOU_SWITCH_CLK 40 - 80 MHz */
31 #define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x or IOU_SWITCH_CLK 80 - 120 MHz */
32 #define XLNX_GEM_MDC_DIVIDER_64 4 /* cpu_1x or IOU_SWITCH_CLK 120 - 160 MHz */
33 #define XLNX_GEM_MDC_DIVIDER_96 5 /* cpu_1x or IOU_SWITCH_CLK 160 - 240 MHz */
34 #define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x or IOU_SWITCH_CLK 240 - 320 MHz */
35 #define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x or IOU_SWITCH_CLK 320 - 540 MHz */
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| /Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/common/ |
| D | Kconfig.soc | 93 1. Flash SPI running at 40MHz and RAM SPI running at 40MHz
94 2. Flash SPI running at 80MHz and RAM SPI running at 40MHz
95 3. Flash SPI running at 80MHz and RAM SPI running at 80MHz
97 …Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI h…
100 option to select 80MHz will only be visible if the flash SPI speed is also 80MHz.
104 bool "26MHz clock speed"
108 bool "20MHz clock speed"
112 bool "40MHz clock speed"
116 bool "80MHz clock speed"
120 bool "120MHz clock speed"
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| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | spi_esp32_spim.h | 17 #define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) /* 8.89MHz */
18 #define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) /* 10MHz */
19 #define SPI_MASTER_FREQ_11M (APB_CLK_FREQ/7) /* 11.43MHz */
20 #define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/6) /* 13.33MHz */
21 #define SPI_MASTER_FREQ_16M (APB_CLK_FREQ/5) /* 16MHz */
22 #define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/4) /* 20MHz */
23 #define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) /* 26.67MHz */
24 #define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) /* 40MHz */
25 #define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) /* 80MHz */
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| /Zephyr-Core-3.5.0/soc/arm/nuvoton_npcx/ |
| D | Kconfig | 56 bool "SPI flash max clock rate of 20 MHz"
59 bool "SPI flash max clock rate of 25 MHz"
62 bool "SPI flash max clock rate of 33 MHz"
66 bool "SPI flash max clock rate of 40 MHz"
69 bool "SPI flash max clock rate of 50 MHz"
77 default 40 if NPCX_HEADER_SPI_MAX_CLOCK_40
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| /Zephyr-Core-3.5.0/soc/nios2/nios2f-zephyr/cpu/ |
| D | ghrd_10m50da.qsf | 200 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[0]
201 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[2]
202 set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_pb[1]
231 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[0] -ta…
233 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[1] -ta…
235 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[2] -ta…
237 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[3] -ta…
239 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[4] -ta…
241 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[5] -ta…
243 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[6] -ta…
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| /Zephyr-Core-3.5.0/dts/bindings/can/ |
| D | ti,tcan4x5x.yaml | 43 TCAN4x5x oscillator clock frequency in Hz (20MHz or 40MHz).
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| D | microchip,mcp251xfd.yaml | 69 is not set, then an internal clock (typically 40MHz or 20MHz) will be
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| /Zephyr-Core-3.5.0/samples/boards/ti/cc13x2_cc26x2/system_off/src/ |
| D | ext_flash.c | 42 * 3 cycles per loop: 8 loops @ 48 Mhz = 0.5 us. in CC1352R1_LAUNCHXL_sendExtFlashByte()
51 * Keep CS high at least 40 us in CC1352R1_LAUNCHXL_sendExtFlashByte()
52 * 3 cycles per loop: 700 loops @ 48 Mhz ~= 44 us in CC1352R1_LAUNCHXL_sendExtFlashByte()
69 /* 3 cycles per loop: 1 loop @ 48 Mhz ~= 62 ns */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
72 /* 3 cycles per loop: 560 loops @ 48 Mhz ~= 35 us */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
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| /Zephyr-Core-3.5.0/dts/bindings/sensor/ |
| D | ti,fdc2x1x.yaml | 46 The internal clock oscillates at around 43360 KHz (43.36 MHz)
48 Recommended external clock source frequency is 40000 KHz (40 MHz).
97 1 = 1MHz
98 4 = 3.3MHz
99 5 = 10MHz
100 7 = 33MHz
234 0.01MHz and 8.75MHz
235 2 = divide by 2. Choose for sensor frequencies between 5MHz
236 and 10MHz
240 0.01MHz and 10MHz
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| /Zephyr-Core-3.5.0/soc/arm/ti_lm3s6965/ |
| D | soc.h | 22 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(12)
63 #define IRQ_RESERVED4 40
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| /Zephyr-Core-3.5.0/boards/sparc/generic_leon3/doc/ |
| D | index.rst | 48 Detected frequency: 50.0 MHz
70 400040A8 initlevel 40B [===============>] 100%
100 system frequency: 50.000 MHz
109 section: initlevel, addr: 0x400040a8, size 40 bytes
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| /Zephyr-Core-3.5.0/boards/arm/nucleo_l412rb_p/doc/ |
| D | index.rst | 31 - 24 MHz HSE
55 - -40 °C to 85/125 °C temperature range
61 - 79 |micro| A/MHz run mode (LDO Mode)
62 - 28 |micro| A/MHz run mode (@3.3 V SMPS Mode)
68 …e| ) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and …
71 - 1.25 DMIPS/MHz (Drystone 2.1)
72 - 273.55 CoreMark |reg| (3.42 CoreMark/MHz @ 80 MHz)
81 - 4 to 48 MHz crystal oscillator
83 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
85 …- Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than |plusminus| 0…
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| /Zephyr-Core-3.5.0/boards/arm/nucleo_u5a5zj_q/doc/ |
| D | index.rst | 38 They operate at a frequency of up to 160 MHz.
44 - -40 °C to +85/125 °C temperature range
51 - 2 µA Stop 3 mode with 40-Kbyte SRAM
53 - 4.65 µA Stop 2 mode with 40-Kbyte SRAM
55 - 18.5 µA/MHz Run mode at 3.3 V
62 memories: frequency up to 160 MHz, 240 DMIPS
72 - 1.5 DMIPS/MHz (Drystone 2.1)
73 - 655 CoreMark® (4.09 CoreMark®/MHz)
87 - 16-bit HSPI memory interface up to 160 MHz
107 - 4 to 50 MHz crystal oscillator
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| /Zephyr-Core-3.5.0/modules/hal_gigadevice/ |
| D | Kconfig | 43 bool "8MHz"
46 Use 8MHz oscillator for HXTAL
49 bool "25MHz"
52 Use 25MHz oscillator for HXTAL
64 Use 40KHz oscillator for low speed internal RC Oscillator
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| /Zephyr-Core-3.5.0/boards/arm/stm32g071b_disco/ |
| D | stm32g071b_disco.dts | 143 vbus_meas: ina230@40 {
160 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
163 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
164 * range is 9 <--> 18 MHz.
166 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
173 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
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| /Zephyr-Core-3.5.0/boards/arm/raytac_mdbt53v_db_40_nrf5340/doc/ |
| D | index.rst | 3 Raytac MDBT53V-DB-40
9 Raytac MDBT53V-DB-40 demo board is a development board based on the Raytac MDBT53V-1M module,
18 Armv8-M Security Extension, running at up to 128 MHz, referred to as
21 at a fixed 64 MHz, referred to as the **network core**.
48 .. figure:: img/MDBT53V-DB-40.jpg
51 :alt: MDBT53V-DB-40
53 MDBT53V-DB-40 (Credit: Raytac Corporation)
55 More information about the board can be found at the `MDBT53V-DB-40 website`_.
56 The `MDBT53V-DB-40 Specification`_ contains the demo board's datasheet.
57 The `MDBT53V-DB-40 Schematic`_ contains the demo board's schematic.
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| /Zephyr-Core-3.5.0/drivers/ieee802154/ |
| D | ieee802154_dw1000_regs.h | 126 /* System Time Counter (40-bit) */
129 /* Note 40 bit register */
136 /* Note 40 bit register */
170 /* Transmit Pulse Repetition Frequency = 4 Mhz */
172 /* Transmit Pulse Repetition Frequency = 16 Mhz */
174 /* Transmit Pulse Repetition Frequency = 64 Mhz */
212 /* Delayed Send or Receive Time (40-bit) */
328 /* Note 40 bit register */
557 /* Note 40 bit register */
577 /* read only 5 bytes (the adjusted timestamp (40:0)) */
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| /Zephyr-Core-3.5.0/boards/arm/raytac_mdbt53_db_40_nrf5340/doc/ |
| D | index.rst | 3 Raytac MDBT53-DB-40
9 Raytac MDBT53-DB-40 demo board is a development board based on the Raytac MDBT53-1M module,
18 Armv8-M Security Extension, running at up to 128 MHz, referred to as
21 at a fixed 64 MHz, referred to as the **network core**.
49 .. figure:: img/MDBT53-DB-40.jpg
52 :alt: MDBT53-DB-40
54 MDBT53-DB-40 (Credit: Raytac Corporation)
56 More information about the board can be found at the `MDBT53-DB-40 website`_.
57 The `MDBT53-DB-40 Specification`_ contains the demo board's datasheet.
58 The `MDBT53-DB-40 Schematic`_ contains the demo board's schematic.
[all …]
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| /Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/kwx/ |
| D | soc_kw4xz.c | 84 /* Initialize system clock to 40 MHz */ in kwx_init()
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| /Zephyr-Core-3.5.0/drivers/audio/ |
| D | tlv320dac310x.h | 33 #define DAC_PROC_CLK_FREQ_MAX 49152000 /* 49.152 MHz */
41 #define DAC_MOD_CLK_FREQ_MIN 2800000 /* 2.8 MHz */
42 #define DAC_MOD_CLK_FREQ_MAX 6200000 /* 6.2 MHz */
116 #define HPL_DRV_GAIN_CTRL_ADDR (struct reg_addr){1, 40}
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| /Zephyr-Core-3.5.0/boards/arm/sensortile_box/doc/ |
| D | index.rst | 32 execution from Flash memory, frequency up to 120 MHz, MPU, 150
33 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
36 - 16 MHz crystal oscillator
103 driven by the PLL clock at 80MHz, driven by the 16MHz external oscillator.
104 The system clock can be boosted to 120MHz.
105 The internal AHB/APB1/APB2 AMBA buses are all clocked at 80MHz.
200 …https://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0…
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| /Zephyr-Core-3.5.0/dts/bindings/clock/ |
| D | st,stm32-rcc.yaml | 20 clocks = <&pll>; /* Select 80MHz pll as SYSCLK source */
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
129 (>80MHz) in two steps in order to prevent undershoot.
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| /Zephyr-Core-3.5.0/boards/arm/wio_terminal/doc/ |
| D | index.rst | 11 USB C port, FPC connector, microSD card slot, Raspberry Pi compatible 40-pins
22 - ATSAMD51P19 ARM Cortex-M4F processor at 120 MHz
33 - GPIO 40 pin (Raspberry Pi compatible)
112 on-chip PLL generating the 120 MHz system clock.
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| /Zephyr-Core-3.5.0/boards/arm/stm32l476g_disco/doc/ |
| D | index.rst | 56 - Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode)
57 … |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhryst…
59 - 4 to 48 MHz crystal oscillator
61 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
63 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
67 - LCD 8 x 40 or 4 x 44 with step-up converter
152 as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz,
153 driven by 16MHz high speed internal oscillator.
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