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/Zephyr-Core-3.5.0/tests/lib/c_lib/src/
Dtest_qsort.c78 1, 18, -78, 35, -67, -71, -12, -69, -60, 91, -15, -99, -33, in ZTEST()
79 -52, 52, -4, -89, -7, 22, -52, -87, 32, -23, 30, -35, -9, in ZTEST()
81 35, -5, -72, -46, 64, -46, -97, -88, 90, 63, 49, 12, -58, in ZTEST()
88 -63, -61, -60, -58, -52, -52, -49, -46, -46, -42, -42, -35, -33, in ZTEST()
90 18, 22, 24, 30, 32, 35, 35, 36, 41, 42, 42, 49, 49, in ZTEST()
105 1, 18, -78, 35, -67, -71, -12, -69, -60, 91, -15, -99, -33, -52, in ZTEST()
106 52, -4, -89, -7, 22, -52, -87, 32, -23, 30, -35, -9, 15, -61, in ZTEST()
107 36, -49, 24, -72, -63, 77, 88, -93, 13, 49, 41, 35, -5, -72, in ZTEST()
118 -45, -42, -42, -40, -35, -33, -27, -23, -21, -15, -12, -11, -9, -9, in ZTEST()
120 18, 22, 24, 24, 27, 30, 32, 33, 35, 35, 36, 38, 40, 41, in ZTEST()
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/sam4s/
DKconfig.defconfig.series26 # SAM4S family has total 35 peripherals capable of
30 default 35
/Zephyr-Core-3.5.0/boards/riscv/litex_vexriscv/doc/
Dindex.rst19 `Digilent Arty A7-35T or A7-100T Development Boards
25 :alt: LiteX VexRiscv on Digilent Arty 35T Board
47 bitstream for the FPGA on a Digilent Arty A7-35 Board or SDI-MIPI Video Converter. This can be achi…
70 …Generating the bitstream for the Digilent Arty A7-35 Board requires F4PGA toolchain installation. …
90 #. Set up the F4PGA environment (for the Digilent Arty A7-35 Board):
100 #. Generate the bitstream for the Arty 35T:
104 ./make.py --board=arty --variant=a7-35 --build --toolchain=symbiflow
170 To upload the bitstream to Digilent Arty A7-35 you can use `xc3sprog <https://github.com/matrix-io/…
/Zephyr-Core-3.5.0/dts/bindings/sensor/
Dmaxim,max31875.yaml38 A resolution of 10 bits takes 35ms to convert.
49 - 10 # 35
/Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/common/
Dpinctrl_soc.h143 #define MIO35 35
165 #define MIO_GROUP_ETHERNET1_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
192 #define MIO_GROUP_SPI1_2_GRP_PINS 34, 35, 36
205 #define MIO_GROUP_SDIO1_2_GRP_PINS 34, 35, 36, 37, 38, 39
213 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
224 #define MIO_GROUP_CAN0_6_GRP_PINS 34, 35
247 #define MIO_GROUP_UART0_6_GRP_PINS 34, 35
270 #define MIO_GROUP_I2C0_6_GRP_PINS 34, 35
332 #define MIO_GROUP_GPIO0_35_GRP_PINS 35
351 #define MIO_GROUP_USB0_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
/Zephyr-Core-3.5.0/samples/net/sockets/websocket_client/
Dsample.yaml8 min_ram: 35
/Zephyr-Core-3.5.0/boards/arm/legend/
Drevision.cmake1 set(LEGEND_REVISIONS "25hdd" "25ssd" "35")
/Zephyr-Core-3.5.0/drivers/pinctrl/
DKconfig.rv32m113 default 35
/Zephyr-Core-3.5.0/dts/bindings/led/
Dti,lp50xx.yaml14 If enabled the maximum current output is set to 35 mA (25.5 mA else).
/Zephyr-Core-3.5.0/drivers/reset/
DKconfig21 default 35
/Zephyr-Core-3.5.0/samples/boards/ti/cc13x2_cc26x2/system_off/src/
Dext_flash.c64 * least 20 ns and ten wait at least 35 us. in CC1352R1_LAUNCHXL_wakeUpExtFlash()
72 /* 3 cycles per loop: 560 loops @ 48 Mhz ~= 35 us */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
/Zephyr-Core-3.5.0/drivers/dai/intel/alh/
Dalh_map.h42 35, /* 26 - BIDIRECTIONAL */
51 -1, /* 35 - INVALID */
/Zephyr-Core-3.5.0/drivers/fuel_gauge/bq27z746/
Demul_bq27z746.c58 * 35: Length including command, checksum and length (e.g. data length + 4) in emul_bq27z746_read_altmac()
69 buf[35] = sizeof(manufacturer_name) - 1 + BQ27Z746_MAC_OVERHEAD_LEN; in emul_bq27z746_read_altmac()
73 buf[35] = sizeof(device_name) - 1 + BQ27Z746_MAC_OVERHEAD_LEN; in emul_bq27z746_read_altmac()
77 buf[35] = sizeof(device_chemistry) - 1 + BQ27Z746_MAC_OVERHEAD_LEN; in emul_bq27z746_read_altmac()
/Zephyr-Core-3.5.0/tests/bsim/bluetooth/host/misc/disable/src/
Dmain_disable.c17 #define NUM_ITERATIONS 35
/Zephyr-Core-3.5.0/dts/arm/atmel/
Ddma_atmel_same70.h44 #define DMA_PERID_AFEC0_RX 35
Ddma_atmel_samv71.h45 #define DMA_PERID_AFEC0_RX 35
/Zephyr-Core-3.5.0/samples/subsys/nvs/
Dsample.yaml20 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 \
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dti,boosterpack-header.yaml22 6 Analog 26 Analog 35 GPIO 15 SPI MOSI
/Zephyr-Core-3.5.0/soc/arm/ti_lm3s6965/
Dsoc.h58 #define IRQ_TIMER3A 35
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/interrupt-controller/
Desp-esp32c3-intmux.h45 #define TG1_WDT_LEVEL_INTR_SOURCE 35
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/clock/
Dr8a7795_cpg_mssr.h48 #define R8A7795_CLK_SSPRS 35
/Zephyr-Core-3.5.0/boards/arm/arty/doc/
Dindex.rst17 .. figure:: arty_a7-35.jpg
19 :alt: Digilent Arty A7-35
21 Digilent Arty A7-35 (Credit: Digilent Inc)
138 Artix-35T FPGA. For other Arty variants (e.g. the Arty A7-100) the bitstream
/Zephyr-Core-3.5.0/tests/lib/cmsis_nn/src/
Dmain.c41 102, 110, 24, 52, 121, 13, -55, -79, -92, -35, -103, 86, 95, 46, 32,
48 -75, -35, 49, 44, -2, -39, -63, 44, 13, 24, -49, -60, -12, 39, 73,
49 11, -60, 41, 25, 98, 35, -37, -19, 8, 69, 79, 2, -6, -42, 69};
128 95, 62, -38, -32, -35, -105, -53, 70, 112, 14, -4, -33, -26, -93, -98,
135 -90, -8, 110, 37, 35, 124, -123, 94, -122, -114, 37, 85, -36, 53, -40,
137 17, 77, 114, 120, -83, -96, 75, -12, -27, 3, 35, 85, 4, 119, -20,
138 28, 99, 104, -78, -51, -82, -92, -40, -116, 35, -107, 39, 9, -120, -50,
262 95, 91, -66, -80, 114, -49, 7, -67, -35, -1, -88, -77, -56, -103, 5, -39, -118,
445 -1, -115, -123, 75, -75, 68, 52, 12, -35, 116, -68, 22, 15, 76, -81};
/Zephyr-Core-3.5.0/samples/boards/up_squared/gpio_counter/src/
Dmain.c22 * as a 4-bit value (bin 0, 1, 2, 3 -> HAT Pin 35, 37, 38, 40).
48 .hat_num = 35,
/Zephyr-Core-3.5.0/boards/shields/buydisplay_3_5_tft_touch_arduino/
Dbuydisplay_3_5_tft_touch_arduino.overlay41 ngamctrl = [00 16 19 03 0f 05 32 45 46 04 0e 0d 35 37 0f];

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