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/Zephyr-Core-3.7.0/boards/arm/v2m_musca_b1/
Dv2m_musca_b1-common.dtsi10 interrupts = <6 3>;
16 interrupts = <7 3>;
22 interrupts = <3 3>;
28 interrupts = <39 3 40 3 41 3 43 3>;
37 interrupts = <45 3 46 3 47 3 49 3>;
46 interrupts = <67 3 /* combined */
47 51 3 52 3 53 3 54 3 /* PINS 0:3 */
48 55 3 56 3 57 3 58 3 /* PINS 4:7 */
49 59 3 60 3 61 3 62 3 /* PINS 8:11 */
50 63 3 64 3 65 3 66 3>; /* PINS 12:15 */
/Zephyr-Core-3.7.0/boards/arm/v2m_musca_s1/
Dv2m_musca_s1-common.dtsi10 interrupts = <6 3>;
16 interrupts = <7 3>;
22 interrupts = <33 3>;
28 interrupts = <39 3 40 3 41 3 43 3>;
37 interrupts = <45 3 46 3 47 3 49 3>;
46 interrupts = <67 3 /* combined */
47 51 3 52 3 53 3 54 3 /* PINS 0:3 */
48 55 3 56 3 57 3 58 3 /* PINS 4:7 */
49 59 3 60 3 61 3 62 3 /* PINS 8:11 */
50 63 3 64 3 65 3 66 3>; /* PINS 12:15 */
/Zephyr-Core-3.7.0/drivers/pinctrl/renesas/rcar/
Dpfc_r8a77951.c32 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
36 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
37 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
38 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
39 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
40 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
41 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
42 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
43 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
47 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
[all …]
Dpfc_r8a77961.c32 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
36 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
37 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
38 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
39 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
40 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
41 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
42 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
43 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
47 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
[all …]
Dpfc_r8a779f0.c15 { RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */
16 { RCAR_GP_PIN(0, 6), 24, 3 }, /* RX0 */
17 { RCAR_GP_PIN(0, 5), 20, 3 }, /* HRTS0_N */
18 { RCAR_GP_PIN(0, 4), 16, 3 }, /* HCTS0_N */
19 { RCAR_GP_PIN(0, 3), 12, 3 }, /* HTX0 */
20 { RCAR_GP_PIN(0, 2), 8, 3 }, /* HRX0 */
21 { RCAR_GP_PIN(0, 1), 4, 3 }, /* HSCK0 */
22 { RCAR_GP_PIN(0, 0), 0, 3 }, /* SCIF_CLK */
26 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF0_SS1 */
27 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF0_SCK */
[all …]
/Zephyr-Core-3.7.0/tests/kconfig/functions/src/
Dmain.c15 zassert_equal(CONFIG_KCONFIG_ARITHMETIC_ADD_10_3, 10 + 3); in ZTEST()
16 zassert_equal(CONFIG_KCONFIG_ARITHMETIC_ADD_10_3_2, 10 + 3 + 2); in ZTEST()
18 zassert_equal(CONFIG_KCONFIG_ARITHMETIC_SUB_10_3, 10 - 3); in ZTEST()
19 zassert_equal(CONFIG_KCONFIG_ARITHMETIC_SUB_10_3_2, 10 - 3 - 2); in ZTEST()
21 zassert_equal(CONFIG_KCONFIG_ARITHMETIC_MUL_10_3, 10 * 3); in ZTEST()
22 zassert_equal(CONFIG_KCONFIG_ARITHMETIC_MUL_10_3_2, 10 * 3 * 2); in ZTEST()
24 zassert_equal(CONFIG_KCONFIG_ARITHMETIC_DIV_10_3, 10 / 3); in ZTEST()
25 zassert_equal(CONFIG_KCONFIG_ARITHMETIC_DIV_10_3_2, 10 / 3 / 2); in ZTEST()
27 zassert_equal(CONFIG_KCONFIG_ARITHMETIC_MOD_10_3, 10 % 3); in ZTEST()
28 zassert_equal(CONFIG_KCONFIG_ARITHMETIC_MOD_10_3_2, 10 % 3 % 2); in ZTEST()
[all …]
/Zephyr-Core-3.7.0/tests/kconfig/functions/
DKconfig10 default $(add, 10, 3)
14 default $(add, 10, 3, 2)
22 default $(sub, 10, 3)
26 default $(sub, 10, 3, 2)
34 default $(mul, 10, 3)
38 default $(mul, 10, 3, 2)
46 default $(div, 10, 3)
50 default $(div, 10, 3, 2)
58 default $(mod, 10, 3)
62 default $(mod, 10, 3, 2)
[all …]
/Zephyr-Core-3.7.0/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/
Dservice_a_1.c43 '1', '1', '1', '1', '1', '2', '2', '2', '2', '2', '3', '3', '3',
44 '3', '3', '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6',
47 '1', '1', '1', '2', '2', '2', '2', '2', '3', '3', '3', '3', '3',
51 '1', '2', '2', '2', '2', '2', '3', '3', '3', '3', '3', '4', '4',
55 '2', '2', '2', '2', '3', '3', '3', '3', '3', '4', '4', '4', '4',
59 '2', '2', '3', '3', '3', '3', '3', '4', '4', '4', '4', '4', '5',
63 '3', '3', '3', '3', '3', '4', '4', '4', '4', '4', '5', '5', '5',
66 '0', '1', '1', '1', '1', '1', '2', '2', '2', '2', '2', '3', '3',
67 '3', '3', '3', '4', '4', '4', '4', '4', '5', '5', '5', '5', '5',
70 '1', '1', '1', '1', '2', '2', '2', '2', '2', '3', '3', '3', '3',
[all …]
/Zephyr-Core-3.7.0/tests/net/lib/lwm2m/interop/pytest/
Dtest_lwm2m.py94 assert leshan.read(endpoint, '3/0/0') == 'Zephyr'
95 assert leshan.read(endpoint, '3/0/1') == 'client-1'
96 assert leshan.read(endpoint, '3/0/2') == 'serial-1'
100 ''' Verify that Device object match Configuration 3 '''
104 assert resp[0][3] == '1.2.3'
109 ''' Verify that server object match Configuration 3 '''
113 assert obj[0][3] == 10
122 resp = leshan.read(endpoint,'3/0')
130 resp = leshan.read(endpoint, '3/0')
139 leshan.write(endpoint, '1/0/3', 1010)
[all …]
/Zephyr-Core-3.7.0/dts/arm/nuvoton/npcx/
Dnpcx-miwus-wui-map.dtsi23 wui_io83: wui0-1-3 {
24 miwus = <&miwu0 0 3>; /* GPIO83 */
40 wui_io93: wui0-2-3 {
41 miwus = <&miwu0 1 3>; /* GPIO93 */
57 wui_io96: wui0-3-0 {
60 wui_io97: wui0-3-1 {
63 wui_ioa0: wui0-3-2 {
66 wui_ioa1: wui0-3-3 {
67 miwus = <&miwu0 2 3>; /* GPIOA1 */
69 wui_ioa2: wui0-3-4 {
[all …]
/Zephyr-Core-3.7.0/soc/microchip/mec/common/reg/
Dmec_peci.h26 #define MCHP_PECI_CTRL_RST_POS 3
46 #define MCHP_PECI_STS1_RDY_POS 3
65 #define MCHP_PECI_STS2_RFE_POS 3
119 uint8_t RSVD1[3];
121 uint8_t RSVD2[3];
123 uint8_t RSVD3[3];
125 uint8_t RSVD4[3];
127 uint8_t RSVD5[3];
129 uint8_t RSVD6[3];
131 uint8_t RSVD7[3];
[all …]
/Zephyr-Core-3.7.0/include/zephyr/dt-bindings/clock/
Dstm32g4_clock.h54 * - reg (1/2/3) [ 0 : 7 ]
79 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
80 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
81 #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG)
82 #define USART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR_REG)
83 #define USART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG)
84 #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
85 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
86 #define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
87 #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG)
[all …]
Dstm32u5_clock.h62 * - reg (1/2/3) [ 0 : 7 ]
88 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR1_REG)
89 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR1_REG)
90 #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR1_REG)
91 #define UART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR1_REG)
92 #define UART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR1_REG)
93 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR1_REG)
94 #define I2C2_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR1_REG)
95 #define I2C4_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR1_REG)
96 #define SPI2_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR1_REG)
[all …]
Dstm32l4_clock.h52 * - reg (1/2/3) [ 0 : 7 ]
77 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
78 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
79 #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG)
80 #define UART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR_REG)
81 #define UART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG)
82 #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
83 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
84 #define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
85 #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG)
[all …]
/Zephyr-Core-3.7.0/include/zephyr/dt-bindings/pinctrl/
Dambiq-apollo3-pinctrl.h22 #define GPIO_P0 APOLLO3_PINMUX(0, 3)
28 #define GPIO_P1 APOLLO3_PINMUX(1, 3)
34 #define GPIO_P2 APOLLO3_PINMUX(2, 3)
37 #define UA0RTS_P3 APOLLO3_PINMUX(3, 0)
38 #define SLNCE_P3 APOLLO3_PINMUX(3, 1)
39 #define NCE3_P3 APOLLO3_PINMUX(3, 2)
40 #define GPIO_P3 APOLLO3_PINMUX(3, 3)
41 #define MSPI0_7_P3 APOLLO3_PINMUX(3, 5)
42 #define TRIG1_P3 APOLLO3_PINMUX(3, 6)
43 #define I2SWCLK_P3 APOLLO3_PINMUX(3, 7)
[all …]
/Zephyr-Core-3.7.0/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a779f0.h16 #define PIN_HTX0 RCAR_GP_PIN(0, 3)
37 #define PIN_GP1_03 RCAR_GP_PIN(1, 3)
62 #define PIN_QSPI1_SSL RCAR_GP_PIN(2, 3)
76 #define PIN_TSN1_MDIO RCAR_GP_PIN(3, 0)
77 #define PIN_TSN2_MDIO RCAR_GP_PIN(3, 1)
78 #define PIN_TSN0_MDIO RCAR_GP_PIN(3, 2)
79 #define PIN_TSN2_MDC RCAR_GP_PIN(3, 3)
80 #define PIN_TSN0_MDC RCAR_GP_PIN(3, 4)
81 #define PIN_TSN1_MDC RCAR_GP_PIN(3, 5)
82 #define PIN_TSN1_LINK RCAR_GP_PIN(3, 6)
[all …]
/Zephyr-Core-3.7.0/drivers/audio/
Dtas6422dac.h22 #define MODE_CTRL_CH1_LO_MODE BIT(3)
23 #define MODE_CTRL_CH1_LO_MODE_MASK BIT(3)
36 #define MISC_CTRL_1_OTW_CONTROL_110_DEGREE 3
44 #define MISC_CTRL_1_VOLUME_RATE_1_STEP_EVERY_8_FSYNC 3
50 #define MISC_CTRL_1_GAIN_29_V_PEAK_OUTPUT 3
54 #define MISC_CTRL_2_PWM_FREQUENCY_MASK (BIT_MASK(3) << 4)
67 #define MISC_CTRL_2_OUTPUT_PHASE_240_DEGREES 3
80 #define SAP_CTRL_TDM_SLOT_SELECT_2 BIT(3)
81 #define SAP_CTRL_TDM_SLOT_SELECT_2_MASK BIT(3)
82 #define SAP_CTRL_INPUT_FORMAT_MASK BIT_MASK(3)
[all …]
/Zephyr-Core-3.7.0/modules/hal_nordic/nrfx/
Dnrfx_config_nrf51.h18 * Integer value. Minimum: 0 Maximum: 3
21 #define NRFX_DEFAULT_IRQ_PRIORITY 3
36 * Integer value. Minimum: 0 Maximum: 3
59 * - Info = 3
63 #define NRFX_ADC_CONFIG_LOG_LEVEL 3
100 * Integer value. Minimum: 0 Maximum: 3
123 * - Info = 3
127 #define NRFX_CLOCK_CONFIG_LOG_LEVEL 3
142 * Integer value. Minimum: 0 Maximum: 3
174 * - Info = 3
[all …]
/Zephyr-Core-3.7.0/dts/arm/infineon/cat3/xmc/
Dxmc4500_F100x1024-intc.dtsi12 XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */
16 XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */
18 XMC4XXX_INTC_SET_LINE_MAP(2, 3, 2, 1) /* ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 */
28 XMC4XXX_INTC_SET_LINE_MAP(0, 11, 2, 3) /* ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 */
29 XMC4XXX_INTC_SET_LINE_MAP(1, 1, 0, 3) /* ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 */
30 XMC4XXX_INTC_SET_LINE_MAP(3, 6, 1, 3) /* ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 */
31 XMC4XXX_INTC_SET_LINE_MAP(0, 2, 7, 3) /* ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 */
32 XMC4XXX_INTC_SET_LINE_MAP(0, 6, 6, 3) /* ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 */
33 XMC4XXX_INTC_SET_LINE_MAP(1, 0, 4, 3) /* ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 */
34 XMC4XXX_INTC_SET_LINE_MAP(3, 5, 5, 3) /* ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 */
[all …]
Dxmc4700_F144x2048-intc.dtsi12 XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */
16 XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */
18 XMC4XXX_INTC_SET_LINE_MAP(2, 3, 2, 1) /* ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 */
29 XMC4XXX_INTC_SET_LINE_MAP(0, 11, 2, 3) /* ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 */
30 XMC4XXX_INTC_SET_LINE_MAP(1, 1, 0, 3) /* ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 */
31 XMC4XXX_INTC_SET_LINE_MAP(3, 6, 1, 3) /* ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 */
32 XMC4XXX_INTC_SET_LINE_MAP(0, 2, 7, 3) /* ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 */
33 XMC4XXX_INTC_SET_LINE_MAP(0, 6, 6, 3) /* ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 */
34 XMC4XXX_INTC_SET_LINE_MAP(1, 0, 4, 3) /* ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 */
35 XMC4XXX_INTC_SET_LINE_MAP(3, 5, 5, 3) /* ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 */
[all …]
/Zephyr-Core-3.7.0/dts/arm/broadcom/
Dviper-m7.dtsi31 arm,num-irq-priority-bits = <3>;
35 interrupts = <1 3>;
39 interrupts = <203 3>;
44 interrupts = <44 3>, <46 3>, <98 3>, <99 3>, <215 3>;
51 interrupts = <228 3>;
/Zephyr-Core-3.7.0/soc/ene/kb1200/reg/
Dgpio.h15 volatile uint32_t Reserved1[3];
17 volatile uint32_t Reserved2[3];
19 volatile uint32_t Reserved3[3];
21 volatile uint32_t Reserved4[3];
23 volatile uint32_t Reserved5[3];
25 volatile uint32_t Reserved6[3];
27 volatile uint32_t Reserved7[3];
29 volatile uint32_t Reserved8[3];
31 volatile uint32_t Reserved9[3];
33 volatile uint32_t Reserved10[3];
[all …]
/Zephyr-Core-3.7.0/subsys/net/ip/
Dnet_tc_mapping.h25 * 3 CA Critical applications
50 #if NET_TC_TX_COUNT == 3 || NET_TC_RX_COUNT == 3
54 static const uint8_t priority2tc_strict_4[] = {0, 0, 1, 1, 2, 2, 3, 3};
57 static const uint8_t priority2tc_strict_5[] = {0, 0, 1, 1, 2, 2, 3, 4};
60 static const uint8_t priority2tc_strict_6[] = {1, 0, 2, 2, 3, 3, 4, 5};
63 static const uint8_t priority2tc_strict_7[] = {1, 0, 2, 3, 4, 4, 5, 6};
66 static const uint8_t priority2tc_strict_8[] = {1, 0, 2, 3, 4, 5, 6, 7};
86 #if NET_TC_TX_COUNT == 3 || NET_TC_RX_COUNT == 3
90 static const uint8_t priority2tc_sr_ab_4[] = {0, 0, 2, 3, 1, 1, 1, 1};
93 static const uint8_t priority2tc_sr_ab_5[] = {0, 0, 3, 4, 1, 1, 2, 2};
[all …]
/Zephyr-Core-3.7.0/dts/arm/infineon/cat1a/legacy/
Dpsoc6_cm0.dtsi34 interrupts = <0 3>;
42 interrupts = <1 3>;
50 interrupts = <2 3>;
53 intmux_ch3: interrupt-controller@3 {
58 interrupts = <3 3>;
66 interrupts = <4 3>;
74 interrupts = <5 3>;
82 interrupts = <6 3>;
90 interrupts = <7 3>;
98 interrupts = <8 3>;
[all …]
/Zephyr-Core-3.7.0/samples/kernel/condition_variables/condvar/
DREADME.rst42 inc_count: thread 3, count = 2, unlocking mutex
43 inc_count: thread 2, count = 3, unlocking mutex
44 inc_count: thread 3, count = 4, unlocking mutex
46 inc_count: thread 3, count = 6, unlocking mutex
48 inc_count: thread 3, count = 8, unlocking mutex
50 inc_count: thread 3, count = 10, unlocking mutex
52 inc_count: thread 3, count = 12 Threshold reached.Just sent signal.
53 inc_count: thread 3, count = 12, unlocking mutex
59 inc_count: thread 3, count = 139, unlocking mutex
61 inc_count: thread 3, count = 141, unlocking mutex
[all …]

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