Searched +full:3 +full:- +full:cell (Results 1 – 25 of 56) sorted by relevance
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9 * SPDX-License-Identifier: Apache-2.020 * @defgroup devicetree-pwms Devicetree PWMs API31 * pwm1: pwm-controller@... { ... };33 * pwm2: pwm-controller@... { ... };37 * <&pwm2 3 PWM_POLARITY_INVERTED>;60 * pwm1: pwm-controller@... { ... };62 * pwm2: pwm-controller@... { ... };66 * <&pwm2 3 PWM_POLARITY_INVERTED>;67 * pwm-names = "alpha", "beta";76 * @param name lowercase-and-underscores name of a pwms element[all …]
9 * SPDX-License-Identifier: Apache-2.020 * @defgroup devicetree-dmas Devicetree DMA API37 * <&dma2 6 3 0x404 0x5>;65 * <&dma2 6 3 0x404 0x5>;66 * dma-names = "tx", "rx";75 * @param name lowercase-and-underscores name of a dmas element76 * as defined by the node's dma-names property109 * @param name lowercase-and-underscores name of a dmas element110 * as defined by the node's dma-names property127 * @brief Get a DMA specifier's cell value at an index[all …]
10 * SPDX-License-Identifier: Apache-2.021 * @defgroup devicetree-gpio Devicetree GPIO API28 * gpio phandle-array property at an index46 * @param gpio_pha lowercase-and-underscores GPIO property with47 * type "phandle-array"59 * @param gpio_pha lowercase-and-underscores GPIO property with60 * type "phandle-array"72 * @brief Get a label property from a gpio phandle-array property99 * @param gpio_pha lowercase-and-underscores GPIO property with100 * type "phandle-array"[all …]
1 .. zephyr:code-sample:: eth-ivshmem2 :name: Inter-VM Shared Memory (ivshmem) Ethernet3 :relevant-api: ivshmem ethernet5 Communicate with another "cell" in the Jailhouse hypervisor using IVSHMEM Ethernet.11 another "cell" in the Jailhouse hypervisor. Currently only the qemu_cortex_a5320 .. code-block:: console22 git clone https://github.com/siemens/jailhouse-images.git23 cd jailhouse-images29 .. code-block:: console31 ./kas-container menu[all …]
1 # SPDX-License-Identifier: BSD-3-Clause3 description: Interrupt controller with one cell5 compatible: "interrupt-one-cell"7 interrupt-cells:8 - one
1 # SPDX-License-Identifier: BSD-3-Clause5 compatible: "interrupt-two-cell"7 interrupt-cells:8 - one9 - two
1 # SPDX-License-Identifier: BSD-3-Clause5 compatible: "interrupt-three-cell"7 interrupt-cells:8 - one9 - two10 - three
9 The LS1046A reference design board (RDB) is a high-performance computing,13 of high-speed SerDes ports.15 The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A7216 cores with packet processing acceleration and high-speed peripherals. The18 Ethernet, PCIe Gen. 3, SATA 3.0, USB 3.0 and QSPI interfaces provides an28 - Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed29 - Supports 8 GB DDR4 SDRAM memory30 - SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi32 - One 512 MB SLC NAND flash with ECC support (1.8 V)33 - CPLD connection: 8-bit registers in CPLD to configure mux/demux selections[all …]
2 # SPDX-License-Identifier: Apache-2.012 - bit 6-7: Direction (see dma.h)13 - 0x0: MEMORY to MEMORY14 - 0x1: MEMORY to PERIPH15 - 0x2: PERIPH to MEMORY16 - 0x3: reserved for PERIPH to PERIPH18 - bit 9: Peripheral address increase19 - 0x0: no address increment between transfers20 - 0x1: increment address between transfers22 - bit 10: Memory address increase[all …]
2 # SPDX-License-Identifier: Apache-2.010 - bit 6-7: Direction (see dma.h)11 - 0x0: MEMORY to MEMORY12 - 0x1: MEMORY to PERIPH13 - 0x2: PERIPH to MEMORY14 - 0x3: reserved for PERIPH to PERIPH16 - bit 9: Peripheral address increase17 - 0x0: no address increment between transfers18 - 0x1: increment address between transfers20 - bit 10: Memory address increase[all …]
2 # SPDX-License-Identifier: Apache-2.010 described in the dma.txt file, using a four-cell specifier for each13 described in the dma.txt file, using a 3-cell specifier for each15 1. channel: the dma stream from 1 to <dma-requests>17 this value is 0 for Memory-to-memory transfers18 or a value between <1> .. <dma-generators> (not supported yet)19 or a value beweeen <dma-generators>+1 .. <dma-generators>+<dma-requests>20 3. channel-config: A 32bit mask specifying the DMA channel configuration23 -bit 5 : DMA cyclic mode config26 -bit 6-7 : Direction (see dma.h)[all …]
2 # SPDX-License-Identifier: Apache-2.09 DMA clients connected to the STM32 DMA controller must use a three-cell17 dma-names = "tx", "rx";20 1. channel: the stream or channel from 0 to (<dma-channels> - 1).22 the slot is a value between <0> .. (<dma-requests> - 1).23 3. channel-config: A 32bit mask specifying the DMA channel configuration25 -bit 6-7 : Direction (see dma.h)30 -bit 9 : Peripheral Increment Address33 -bit 10 : Memory Increment Address36 -bit 11-12 : Peripheral data size[all …]
2 # SPDX-License-Identifier: Apache-2.010 described in the dma.txt file, using a four-cell specifier for each12 1. channel: the dma stream from 0 to <dma-requests>14 this value is 0 for Memory-to-memory transfers15 or a value between <1> .. <dma-generators> (not supported yet)16 or a value beweeen <dma-generators>+1 .. <dma-generators>+<dma-requests>17 3. channel-config: A 32bit mask specifying the DMA channel configuration19 -bit 6-7 : Direction (see dma.h)24 -bit 9 : Peripheral Increment Address27 -bit 10 : Memory Increment Address[all …]
2 # SPDX-License-Identifier: Apache-2.09 DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier11 1. channel: the mux channel from 0 to <dma-channels> - 113 3. channel-config: A 32bit mask specifying the DMA channel configuration15 -bit 6-7 : Direction (see dma.h)20 -bit 9 : Peripheral Increment Address23 -bit 10 : Memory Increment Address26 -bit 11-12 : Peripheral data size28 0x1: Half-word (16 bits)31 -bit 13-14 : Memory data size[all …]
2 # SPDX-License-Identifier: Apache-2.011 described in the dma.txt file, using a 2-cell specifier for each13 1. channel: the dma stream from 1 to <dma-requests>14 2. channel-config: A 32bit mask specifying the DMA channel configuration17 -bit 5 : DMA cyclic mode config20 -bit 6-7 : Direction (see dma.h)25 -bit 9 : Peripheral Increment Address28 -bit 10 : Memory Increment Address31 -bit 11-12 : Peripheral data size33 0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits)[all …]
4 * SPDX-License-Identifier: Apache-2.011 GDMA_TRIG_PERIPH_M2M = -1,15 GDMA_TRIG_PERIPH_I2S0 = 3,32 #define ESP32_DT_INST_DMA_CELL(n, name, cell) \ argument34 (DT_INST_DMAS_CELL_BY_NAME(n, name, cell)), \
2 # SPDX-License-Identifier: Apache-2.06 compatible: "atmel,sam-adc"8 include: [adc-controller.yaml, pinctrl-device.yaml]25 startup-time:32 settling-time:37 or differential input parameters of the analog cell change38 between two channels, the analog cell may need a specific40 enum: [3, 5, 9, 17]42 tracking-time:49 enum: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16][all …]
2 * SPDX-License-Identifier: Apache-2.036 * -----------------39 * part in DT_N_<path-id>_P_<property-id> macros, or the "prop-suf"61 * _IDX_<i>_VAL_<val>_EXISTS: cell value exists, by index65 * _NAME_<name>_VAL_<val>_EXISTS: cell value exists, by name72 * @defgroup devicetree-generic-id Node identifiers and helpers97 * The arguments to this macro are the names of non-root nodes in the99 * Non-alphanumeric characters in each name must be converted to109 * current-speed = <115200>;120 * Example usage with DT_PROP() to get the `current-speed` property:[all …]
4 * SPDX-License-Identifier: BSD-3-Clause9 /dts-v1/;16 interrupt-parent-test {18 compatible = "interrupt-three-cell";19 #interrupt-cells = <3>;20 interrupt-controller;23 interrupts = <1 2 3 4 5 6>;24 interrupt-names = "foo", "bar";25 interrupt-parent = <&{/interrupt-parent-test/controller}>;28 interrupts-extended-test {[all …]
3 NXP i.MX93 EVK (Cortex-A55)9 The i.MX93 Evaluation Kit (MCIMX93-EVK board) is a platform designed to show11 small and low cost package. The MCIMX93-EVK board is an entry-level development15 i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single16 Cortex®-M33 core. Zephyr OS is ported to run on one of the Cortex®-A55 core.18 - Board features:20 - RAM: 2GB LPDDR421 - Storage:23 - SanDisk 16GB eMMC5.124 - microSD Socket[all …]
4 * SPDX-License-Identifier: Apache-2.030 /** Anti-aliased points, point radius is 1-256 pixels */33 * Anti-aliased lines, with width from 0 to 4095 1/16th of pixel units.36 #define FT8XX_LINES 3U37 /** Anti-aliased lines, connected head-to-tail */48 * Round-cornered rectangles, curvature of the corners can be adjusted using57 * - @ref FT8XX_BITMAPS58 * - @ref FT8XX_POINTS59 * - @ref FT8XX_LINES60 * - @ref FT8XX_LINE_STRIP[all …]
1 .. _dt-syntax:6 As the name indicates, a devicetree is a tree. The human-readable text format24 .. code-block:: devicetree26 /dts-v1/;29 a-node {30 subnode_nodelabel: a-sub-node {31 foo = <3>;36 The ``/dts-v1/;`` line means the file's contents are in version 1 of the DTS37 syntax, which has replaced a now-obsolete "version 0".46 #. A node named ``a-node``, which is a child of the root node[all …]
3 compatible: "nordic,nrf-sw-pwm"5 include: [pwm-controller.yaml, base.yaml]14 clock-prescaler:25 channel-gpios:26 type: phandle-array36 sw_pwm: sw-pwm {37 compatible = "nordic,nrf-sw-pwm";39 channel-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>,48 Please note that in the flags cell (the last component of each item56 "#pwm-cells":[all …]
4 * SPDX-License-Identifier: Apache-2.019 /** RCU offset (from id cell) */21 /** RCU configuration bit (from id cell) */28 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U,32 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U,36 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U,73 const struct clock_control_gd32_config *config = dev->config; in clock_control_gd32_on()76 sys_set_bit(config->base + GD32_CLOCK_ID_OFFSET(id), in clock_control_gd32_on()85 const struct clock_control_gd32_config *config = dev->config; in clock_control_gd32_off()88 sys_clear_bit(config->base + GD32_CLOCK_ID_OFFSET(id), in clock_control_gd32_off()[all …]
11 " http://www.apache.org/licenses/LICENSE-2.0\n",43 "<table class=\"tfo-notebook-buttons\" align=\"left\">\n",48 …ic_wand_model.ipynb\"><img src=\"https://www.tensorflow.org/images/GitHub-Mark-32px.png\" />View s…60 …efore you proceed, ensure you are using a GPU runtime by going to **Runtime -> Change runtime type…72 "Run the following cell to ensure the correct version of TensorFlow is used."96 "!git clone --depth 1 -q https://github.com/tensorflow/tensorflow\n",98 "!cp -r tensorflow/tensorflow/lite/micro/examples/magic_wand/train train"126 "!tar xvzf data.tar.gz -C train 1>/dev/null"161 "id": "5-cmVbFvhTvy"181 "%tensorboard --logdir logs/scalars"[all …]
