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/Zephyr-Core-3.4.0/dts/arm/atmel/
Dsamr21.dtsi27 #dma-cells = <2>;
37 #gpio-cells = <2>;
38 #atmel,pin-cells = <2>;
51 clocks = <&gclk 26>, <&pm 0x20 8>;
62 clocks = <&gclk 26>, <&pm 0x20 9>;
65 channels = <2>;
73 clocks = <&gclk 27>, <&pm 0x20 10>;
76 channels = <2>;
84 clocks = <&gclk 0x14>, <&pm 0x20 2>;
90 clocks = <&gclk 0x15>, <&pm 0x20 3>;
[all …]
Dsamd21.dtsi27 #dma-cells = <2>;
32 reg = <0x42003800 0x20>;
34 clocks = <&gclk 0x1d>, <&pm 0x20 14>;
42 clocks = <&gclk 26>, <&pm 0x20 8>;
53 clocks = <&gclk 26>, <&pm 0x20 9>;
56 channels = <2>;
64 clocks = <&gclk 27>, <&pm 0x20 10>;
67 channels = <2>;
75 clocks = <&gclk 33>, <&pm 0x20 18>;
81 clocks = <&gclk 0x14>, <&pm 0x20 2>;
[all …]
Dsamd20.dtsi12 tc-2 = &tc2;
19 reg = <0x42002000 0x20>;
21 clocks = <&gclk 0x13>, <&pm 0x20 8>;
27 reg = <0x42002800 0x20>;
29 clocks = <&gclk 0x14>, <&pm 0x20 10>;
35 reg = <0x42003800 0x20>;
37 clocks = <&gclk 0x16>, <&pm 0x20 14>;
45 clocks = <&gclk 26>, <&pm 0x20 18>;
51 clocks = <&gclk 0xd>, <&pm 0x20 2>;
57 clocks = <&gclk 0xe>, <&pm 0x20 3>;
[all …]
Dsaml21.dtsi23 #dma-cells = <2>;
55 channels = <2>;
81 clocks = <&gclk 20>, <&mclk 0x1c 2>;
99 clocks = <&gclk 24>, <&mclk 0x20 1>;
105 clocks = <&gclk 29>, <&mclk 0x20 2>;
112 clocks = <&gclk 30>, <&mclk 0x20 3>;
Dsamd5x.dtsi48 sercom-2 = &sercom2;
56 tc-2 = &tc2;
62 tcc-2 = &tcc2;
95 #clock-cells = <2>;
123 #dma-cells = <2>;
202 clocks = <&gclk 34>, <&mclk 0x20 0>;
211 clocks = <&gclk 35>, <&mclk 0x20 1>;
220 clocks = <&gclk 36>, <&mclk 0x20 2>;
229 clocks = <&gclk 37>, <&mclk 0x20 3>;
243 #gpio-cells = <2>;
[all …]
/Zephyr-Core-3.4.0/tests/net/ppp/driver/src/
Dmain.c50 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
51 0x7d, 0x26, 0x7d, 0x20, 0x7d, 0x20, 0x7d, 0x20,
52 0x7d, 0x20, 0x7d, 0x25, 0x7d, 0x26, 0x5d, 0x58,
66 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
67 0x7d, 0x26, 0x7d, 0x20, 0x7d, 0x20, 0x7d, 0x20,
68 0x7d, 0x20, 0x7d, 0x25, 0x7d, 0x26, 0x5d, 0x58,
73 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
79 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x24, 0x1c, 0x90, 0x7e
89 0x21, 0x7d, 0x22, 0x7d, 0x21, 0x7d, 0x20, 0x7d,
102 0x7d, 0x23, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
[all …]
/Zephyr-Core-3.4.0/dts/arm/microchip/
Dmec1501hsz.dtsi38 i2c-smb-2 = &i2c_smb_2;
76 sources = <0 1 2 4 5 10 16 17>;
90 interrupts = <3 2>;
94 #gpio-cells=<2>;
100 interrupts = <2 2>;
104 #gpio-cells=<2>;
111 interrupts = <1 2>;
112 port-id = <2>;
114 #gpio-cells=<2>;
121 interrupts = <0 2>;
[all …]
Dmec172xnsz.dtsi80 sources = <0 1 2 3 4 5 6 7
91 sources = <0 1 2 3 4 5 6 7
100 interrupts = <2 0>;
101 girq-id = <2>;
102 sources = <0 1 2 3 4 5 6 7
113 sources = <0 1 2 3 4 5 6 7
124 sources = <0 1 2 3 4 5 6 7
135 sources = <0 1 2 3 4>;
143 sources = <0 1 2 3 4 5 6 7
152 sources = <0 1 2 3 4 5 6 7
[all …]
/Zephyr-Core-3.4.0/drivers/usb/device/
Dusb_dw_registers.h85 uint32_t reserved4[2];
126 #define USB_DW_GINTSTS_OTG_INT BIT(2)
131 #define USB_DW_GRXSTSR_PKT_STS_OUT_DATA 2
144 #define USB_DW_GHWCFG1_EPDIR_MASK(i) (0x3 << (i * 2))
145 #define USB_DW_GHWCFG1_EPDIR_SHIFT(i) (i * 2)
146 #define USB_DW_GHWCFG1_OUTENDPT 2
156 #define USB_DW_GHWCFG2_FSPHYTYPE_FSPLUSUTMI 2
162 #define USB_DW_GHWCFG2_HSPHYTYPE_ULPI 2
180 #define USB_DW_DCFG_DEV_SPD_LS 2
189 #define USB_DW_DSTS_ENUM_LS 2
[all …]
/Zephyr-Core-3.4.0/drivers/sensor/icm42605/
Dicm42605_reg.h18 #define REG_ACCEL_DATA_X0 0x20
92 /* BANK 2 */
148 #define BIT_TEMP_FILT_BW_170 0x20
176 #define SHIFT_INT1_MODE 2
179 #define BIT_TEMP_DIS 0x20
195 #define BIT_DMP_MEM_RESET_EN 0x20
200 #define BIT_COUNT_BIG_ENDIAN 0x20
224 #define BIT_FIFO_WM_TH 0x20
236 #define BIT_INT_PLL_RDY_INT1_EN 0x20
255 #define BIT_TEST_AZ_EN 0x20
[all …]
/Zephyr-Core-3.4.0/dts/arm/nuvoton/npcx/npcx9/
Dnpcx9-miwus-int-map.dtsi20 irq-prio = <2>;
25 irq-prio = <2>;
30 irq-prio = <2>;
35 irq-prio = <2>;
36 group-mask = <0x20>;
40 irq-prio = <2>;
45 irq-prio = <2>;
56 irq-prio = <2>;
57 group-mask = <0x20>;
61 irq-prio = <2>;
/Zephyr-Core-3.4.0/dts/riscv/ite/
Dit81xx2.dtsi26 #gpio-cells = <2>;
39 #gpio-cells = <2>;
52 #gpio-cells = <2>;
75 0x1 0x02 0x20 0x40 >;
76 #pinmux-cells = <2>;
95 #pinmux-cells = <2>;
112 volt-sel-mask = <0x80 0x20 0x10 0
114 #pinmux-cells = <2>;
132 0x40 0x10 0x20 0x40 >;
133 #pinmux-cells = <2>;
[all …]
/Zephyr-Core-3.4.0/tests/crypto/tinycrypt/src/
Dhmac.c76 0x48, 0x69, 0x20, 0x54, 0x68, 0x65, 0x72, 0x65 in ZTEST()
105 0x77, 0x68, 0x61, 0x74, 0x20, 0x64, 0x6f, 0x20, 0x79, 0x61, in ZTEST()
106 0x20, 0x77, in ZTEST()
107 0x61, 0x6e, 0x74, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x6e, 0x6f, in ZTEST()
123 result = do_hmac_test(&h, 2, data, sizeof(data), in ZTEST()
223 0x54, 0x65, 0x73, 0x74, 0x20, 0x57, 0x69, 0x74, 0x68, 0x20, in ZTEST()
232 0x93, 0xf8, 0x60, 0xaa, 0xb0, 0xcd, 0x20, 0xc5 in ZTEST()
275 0x54, 0x65, 0x73, 0x74, 0x20, 0x55, 0x73, 0x69, 0x6e, 0x67, in ZTEST()
276 0x20, 0x4c, in ZTEST()
277 0x61, 0x72, 0x67, 0x65, 0x72, 0x20, 0x54, 0x68, 0x61, 0x6e, in ZTEST()
[all …]
/Zephyr-Core-3.4.0/include/zephyr/arch/nios2/
Dlinker.ld37 * with the exception vector 0x20 bytes after it.
38 * 2. XIP systems where the reset vector is at the beginning of ROM and
56 RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20
57 FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)
60 IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
68 RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20
72 IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
/Zephyr-Core-3.4.0/dts/bindings/gpio/
Draspberrypi-40pins-header.yaml7 The Raspberry Pi layout provides a 2x20 pins header.
14 2 GPIO4 GPIO14/UART0_TXD 3
/Zephyr-Core-3.4.0/include/zephyr/usb/class/
Dusb_cdc.h61 #define SET_LINE_CODING 0x20
73 #define USB_CDC_SERIAL_STATE 0x20
85 #define USB_CDC_SERIAL_STATE_BREAK BIT(2)
105 #define SERIAL_STATE_PARITY 0x20
119 #define USB_CDC_LINE_CODING_STOP_BITS_2 2
123 #define USB_CDC_LINE_CODING_PARITY_EVEN 2
/Zephyr-Core-3.4.0/drivers/video/
Dov2640.c46 #define CTRL2_DCW_EN 0x20
130 #define COM8_BNDF_EN 0x20 /* Enable Banding filter */
199 { COM19, 0x00 }, /* Zoom control 2 LSBs */
215 { 0x20, 0x80 },
236 { 0x42, 0x20 },
252 { BPDATA, 0x20 },
271 { 0x91, 0x20 },
318 { 0xa7, 0x20 },
324 { 0xa7, 0x20 },
330 { 0xa7, 0x20 },
[all …]
/Zephyr-Core-3.4.0/drivers/spi/
Dspi_pw.h73 #define PW_SPI_CTRL1_LBM_BIT BIT(2)
84 #define PW_SPI_CTRL1_SPO_SPH_MASK (BIT_MASK(2) << 3)
87 #define PW_SPI_SSSR_TNF_BIT BIT(2)
102 #define PW_SPI_SITF_HWM_32_ENTRY 0x20
121 #define PW_SPI_SITF_WMRF_32_ENTRY 0x20
132 #define PW_SPI_SITF_HIGH_WM_DFLT 0x20
183 #define PW_SPI_FRAME_SIZE_2_BYTES 2
/Zephyr-Core-3.4.0/soc/xtensa/esp32/
DKconfig.defconfig19 default 0x20
38 default 2
/Zephyr-Core-3.4.0/samples/net/capture/
DREADME.rst54 inet6 2001:db8::2 prefixlen 128 scopeid 0x0<global>
62 inet6 2001:db8:200::2 prefixlen 64 scopeid 0x0<global>
63 inet6 fe80::c000:202 prefixlen 64 scopeid 0x20<link>
71 inet6 fe80::486c:eeff:fead:5d11 prefixlen 64 scopeid 0x20<link>
72 inet6 2001:db8:100::2 prefixlen 64 scopeid 0x0<global>
81 inet6 fe80::5efe:c000:202 prefixlen 64 scopeid 0x20<link>
90 inet6 fe80::387b:a6ff:fe56:6cac prefixlen 64 scopeid 0x20<link>
114 Interface 0x807e040 (Ethernet) [2]
127 IPv6 prefixes (max 2):
133 IPv4 unicast addresses (max 2):
[all …]
/Zephyr-Core-3.4.0/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/
Dadsp_shim.h44 uint32_t dffbrcfd; /* Offset: 0x20 */
60 uint32_t _unused4[2];
77 #define ADSP_DSPWC_OFFSET 0x20
100 #define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
101 #define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
106 #define ADSP_CLKCTL_OSC_SOURCE_MASK (3<<2)
120 #define IOPO_ANCOSEL_FLAG BIT(2)
129 #define GENO_DIOPTOSEL BIT(2)
/Zephyr-Core-3.4.0/tests/net/ipv6/src/
Dmain.c41 static struct in6_addr my_addr = { { { 0x20, 0x01, 0x0d, 0xb8, 0, 0, 0, 0,
43 static struct in6_addr peer_addr = { { { 0x20, 0x01, 0x0d, 0xb8, 0, 0, 0, 0,
45 static struct in6_addr mcast_addr = { { { 0x20, 0x01, 0x0d, 0xb8, 0, 0, 0, 0,
51 0x60, 0x00, 0x00, 0x00, 0x00, 0x20, 0x3A, 0xFF,
52 0x20, 0x01, 0x0D, 0xB8, 0x00, 0x00, 0x00, 0x00,
54 0x20, 0x01, 0x0D, 0xB8, 0x00, 0x00, 0x00, 0x00,
59 0x20, 0x01, 0x0D, 0xB8, 0x00, 0x00, 0x00, 0x00,
82 0x20, 0x01, 0x0D, 0xB8, 0x00, 0x00, 0x00, 0x00,
108 0x20, 0x01, 0x0d, 0xb0, 0x0f, 0xff, 0x00, 0x00,
112 0x20, 0x01, 0x0d, 0xb8, 0x00, 0x00, 0x00, 0x00,
[all …]
/Zephyr-Core-3.4.0/drivers/flash/
Dflash_cadence_qspi_nor_ll.h15 #define CAD_QSPI_ERROR -2
19 #define CAD_QSPI_ADDR_FASTREAD_QUAD_IO 2
22 #define CAT_QSPI_ADDR_QUAD_IO 2
94 #define CAD_QSPI_SELCLKPHASE(x) (FIELD_GET(1, (x)) << 2)
105 #define CAD_QSPI_STIG_OPCODE_SUBSEC_ERASE 0x20
120 #define CAD_QSPI_INST_QUAD 2
125 #define CAD_QSPI_INDRD_RD_STAT(x) (FIELD_GET(1, ((x) >> 2)))
127 #define CAD_QSPI_INDRD_IND_OPS_DONE 0x20
130 #define CAD_QSPI_INDWR_RDSTAT(x) (FIELD_GET(1, ((x) >> 2)))
135 #define CAD_QSPI_INDWR_INDDONE 0x20
/Zephyr-Core-3.4.0/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/
Dadsp_shim.h44 uint32_t dffbrcfd; /* Offset: 0x20 */
60 uint32_t _unused4[2];
77 #define ADSP_DSPWC_OFFSET 0x20
100 #define ADSP_CLKCTL_OSC_SOURCE_MASK (3<<2)
114 #define IOPO_ANCOSEL_FLAG BIT(2)
123 #define GENO_DIOPTOSEL BIT(2)
/Zephyr-Core-3.4.0/tests/drivers/i2c/i2c_api/src/
Dtest_i2c.c48 /* 2. Verify i2c_get_config() */ in test_gy271()
59 datas[1] = 0x20; in test_gy271()
62 if (i2c_write(i2c_dev, datas, 2, 0x1E)) { in test_gy271()
69 if (i2c_write(i2c_dev, datas, 2, 0x1E)) { in test_gy271()
91 datas[0], datas[1], datas[2], in test_gy271()
114 /* 2. Verify i2c_get_config() */ in test_burst_gy271()
125 datas[1] = 0x20; in test_burst_gy271()
126 datas[2] = 0x02; in test_burst_gy271()
146 datas[0], datas[1], datas[2], in test_burst_gy271()

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