| /Zephyr-Core-3.5.0/drivers/interrupt_controller/ |
| D | Kconfig.multilevel | 5 # SPDX-License-Identifier: Apache-2.0
8 bool "Multi-level interrupt support"
13 levels are used, a second level interrupt aggregator would combine
14 all interrupts routed to it into one IRQ line in the first level
15 interrupt controller. If three levels are used, a third level
17 second level. The number of interrupt levels is usually determined
22 int "Total number of first level interrupt bits"
38 config 2ND_LEVEL_INTERRUPTS
39 bool "Second-level interrupt support"
42 Second level interrupts are used to increase the number of
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| D | Kconfig.dw | 2 # SPDX-License-Identifier: Apache-2.0
18 Designware Interrupt Controller can be used as a 2nd level interrupt
20 that is then routed to the 1st level interrupt controller.
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| /Zephyr-Core-3.5.0/include/zephyr/ |
| D | irq.h | 4 * SPDX-License-Identifier: Apache-2.0
14 /* Pull in the arch-specific implementations */
39 * Although this routine is invoked at run-time, all of its arguments must be
46 * @param flags_p Architecture-specific IRQ configuration flags..
60 * @param flags Arch-specific IRQ configuration flags
85 * @param flags Arch-specific IRQ configuration flags
105 * These ISRs are designed for performance-critical interrupt handling and do
114 * - No parameters are passed to the ISR.
115 * - No stack switch is done, the ISR will run on the interrupted context's
117 * - Interrupt locking state is unchanged from how the HW sets it when the ISR
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| /Zephyr-Core-3.5.0/dts/bindings/interrupt-controller/ |
| D | snps,archs-idu-intc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 ARC-HS Interrupt Distribution Unit 2nd-level interrupt controller. Can be
9 compatible: "snps,archs-idu-intc"
11 include: [interrupt-controller.yaml, base.yaml]
13 interrupt-cells:
14 - irq
15 - priority
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| /Zephyr-Core-3.5.0/soc/xtensa/nxp_adsp/common/include/ |
| D | soc.h | 4 * SPDX-License-Identifier: Apache-2.0
22 * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
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| /Zephyr-Core-3.5.0/dts/bindings/dma/ |
| D | st,stm32-bdma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The STM32 BDMA is a general-purpose direct memory access controller
11 described in the dma.txt file, using a four-cell specifier for each
13 1. channel: the bdma stream from 0 to <bdma-requests>
14 2. slot: bdma request
15 3. channel-config: A 32bit mask specifying the BDMA channel configuration
17 -bit 6-7 : Direction (see dma.h)
22 -bit 9 : Peripheral Increment Address
25 -bit 10 : Memory Increment Address
28 -bit 11-12 : Peripheral data size
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/cavs/ |
| D | irq.c | 2 * SPDX-License-Identifier: Apache-2.0
14 #include <cavs-idc.h>
37 case DT_IRQN(CAVS_INTC_NODE(2)): in z_soc_irq_enable()
38 dev_cavs = DEVICE_DT_GET(CAVS_INTC_NODE(2)); in z_soc_irq_enable()
75 case DT_IRQN(CAVS_INTC_NODE(2)): in z_soc_irq_disable()
76 dev_cavs = DEVICE_DT_GET(CAVS_INTC_NODE(2)); in z_soc_irq_disable()
116 case DT_IRQN(CAVS_INTC_NODE(2)): in z_soc_irq_is_enabled()
117 dev_cavs = DEVICE_DT_GET(CAVS_INTC_NODE(2)); in z_soc_irq_is_enabled()
130 ret = -ENODEV; in z_soc_irq_is_enabled()
153 /* extract 2nd level interrupt number */ in z_soc_irq_connect_dynamic()
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| /Zephyr-Core-3.5.0/scripts/build/ |
| D | gen_isr_tables.py | 6 # SPDX-License-Identifier: Apache-2.0
19 # levels of interrupts in a multi-level interrupt system.
20 # 0x000000FF - represents the 1st level (i.e. the interrupts
22 # 0x0000FF00 - represents the 2nd level (i.e. the interrupts funnel
23 # into 1 line which then goes into the 1st level)
24 # 0x00FF0000 - represents the 3rd level (i.e. the interrupts funnel
25 # into 1 line which then goes into the 2nd level)
51 uint32_t num_vectors; <- typically CONFIG_NUM_IRQS
52 struct _isr_list isrs[]; <- Usually of smaller size than num_vectors
65 /** Parameter for non-direct IRQs */
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| /Zephyr-Core-3.5.0/subsys/net/ip/ |
| D | Kconfig.ipv6 | 4 # SPDX-License-Identifier: Apache-2.0
19 default 2 if NET_LOOPBACK
29 default 2
38 default 2
77 default 2
80 Incoming fragments are stored in per-packet queue before being
123 The value depends on your network needs. ND should normally
150 You may disable this option if you wish to implement a non-IP
177 module-dep = NET_LOG
178 module-str = Log level for 6LoWPAN library
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| /Zephyr-Core-3.5.0/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/src/mesh/ |
| D | state_binding.c | 1 /* Bluetooth: Mesh Generic OnOff, Generic Level, Lighting & Vendor Models
5 * SPDX-License-Identifier: Apache-2.0
45 if (light > 0 && light < ctl->light->range_min) { in constrain_lightness()
46 light = ctl->light->range_min; in constrain_lightness()
47 } else if (light > ctl->light->range_max) { in constrain_lightness()
48 light = ctl->light->range_max; in constrain_lightness()
57 if (ctl->light->target > 0 && in constrain_target_lightness2()
58 ctl->light->target < ctl->light->range_min) { in constrain_target_lightness2()
59 if (ctl->light->delta < 0) { in constrain_target_lightness2()
60 ctl->light->target = 0U; in constrain_target_lightness2()
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| /Zephyr-Core-3.5.0/drivers/pwm/ |
| D | pwm_mcux_ftm.c | 3 * Copyright (c) 2020-2021 Vestas Wind Systems A/S
5 * SPDX-License-Identifier: Apache-2.0
23 #define MAX_CHANNELS ARRAY_SIZE(FTM0->CONTROLS)
26 #define MAX_CAPTURE_PAIRS (MAX_CHANNELS / 2U)
27 #define PAIR_1ST_CH(pair) (pair * 2U)
68 const struct mcux_ftm_config *config = dev->config; in mcux_ftm_set_cycles()
69 struct mcux_ftm_data *data = dev->data; in mcux_ftm_set_cycles()
72 uint32_t pair = channel / 2U; in mcux_ftm_set_cycles()
77 LOG_ERR("Channel can not be set to inactive level"); in mcux_ftm_set_cycles()
78 return -ENOTSUP; in mcux_ftm_set_cycles()
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| /Zephyr-Core-3.5.0/arch/xtensa/core/ |
| D | crt1.S | 3 * SPDX-License-Identifier: Apache-2.0
7 * Control arrives here at _start from the reset vector or from crt0-app.S.
39 # define ARG2 a3 /* 2nd outgoing call argument */
47 # define ARG2 a7 /* 2nd outgoing call argument */
58 * _start is typically NOT at the beginning of the text segment --
60 * code that does equivalent initialization (such as crt0-app.S).
63 * - low (level-one) and medium priority interrupts are disabled
65 * - C calling context not initialized:
66 * - PS not initialized
67 * - SP not initialized
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| /Zephyr-Core-3.5.0/arch/arc/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
32 select ARCH_HAS_STACK_PROTECTION if ARC_HAS_STACK_CHECKING || (ARC_MPU && ARC_MPU_VER !=2)
38 v2 ISA for the ARC-HS & ARC-EM cores
66 If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision
67 floating-point extension
73 If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision
74 floating-point and double assist instructions
135 - LPcc instruction
136 - LP_COUNT core reg
137 - LP_START, LP_END aux regs
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| /Zephyr-Core-3.5.0/scripts/native_simulator/common/src/ |
| D | nsi_hw_scheduler.c | 5 * SPDX-License-Identifier: Apache-2.0
55 * Therefore we set SA_RESETHAND: This way, the 2nd time the signal is received
156 * as NSI_TASKS of HW_INIT level.
160 number_of_events = __nsi_hw_events_end - __nsi_hw_events_start; in nsi_hws_init()
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| /Zephyr-Core-3.5.0/arch/xtensa/include/ |
| D | xtensa-asm2-s.h | 4 * SPDX-License-Identifier: Apache-2.0
11 #include "xtensa-asm2-context.h"
23 * A0-A15) to their ABI-defined spill regions on the stack.
31 * and repeats until all but the A0-A3 registers of the original frame
35 * - Vastly smaller code size
37 * - More easily maintained if changes are needed to window over/underflow
40 * - Requires no scratch registers to do its work, so can be used safely in any
43 * - If the WOE bit is not enabled (for example, in code written for
46 * - In memory protection situations, this relies on the existing
53 * - Hilariously it's ACTUALLY FASTER than the HAL routine. And not
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| /Zephyr-Core-3.5.0/drivers/video/ |
| D | ov2640.c | 4 * SPDX-License-Identifier: Apache-2.0
199 { COM19, 0x00 }, /* Zoom control 2 LSBs */
378 /* {HSIZE[11], HSIZE[2:0], VSIZE[2:0]} */
383 { HSIZE, ((UXGA_HSIZE>>2)&0xFF) }, /* H_SIZE[7:0] real/4 */
384 { VSIZE, ((UXGA_VSIZE>>2)&0xFF) }, /* V_SIZE[7:0] real/4 */
406 { 0x00, 0x04, 0x09, 0x00, 0x00 }, /* -2 */
407 { 0x00, 0x04, 0x09, 0x10, 0x00 }, /* -1 */
410 { 0x00, 0x04, 0x09, 0x40, 0x00 }, /* +2 */
416 { 0x00, 0x04, 0x07, 0x20, 0x18, 0x34, 0x06 }, /* -2 */
417 { 0x00, 0x04, 0x07, 0x20, 0x1c, 0x2a, 0x06 }, /* -1 */
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| /Zephyr-Core-3.5.0/arch/xtensa/core/startup/ |
| D | reset-vector.S | 3 * SPDX-License-Identifier: Apache-2.0
10 #include <xtensa/xtensa-xer.h>
11 #include <xtensa/xdm-regs.h>
14 #include <xtensa/xtruntime-core-state.h>
42 .size __start, . - __start
57 #warning "Xtensa TX reset vector not at start of iram0, irom0, or uram0 -- ROMing LSPs may not work"
76 * Even if the processor supports the non-PC-relative L32R option,
77 * it will always start up in PC-relative mode. We take advantage of
78 * this, and use PC-relative mode at least until we're sure the .lit4
81 .begin no-absolute-literals
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/ |
| D | dmic_regs.h | 1 /* SPDX-License-Identifier: Apache-2.0 */
65 /* Common FIFO channels register (primary & secondary) (0000 - 0FFF)
79 * (crossed out) 0010h LOCAL_TSC0 64-bit Wall Clock timestamp
80 * (crossed out) 0018h LOCAL_SAMPLE0 64-bit Sample Count
81 * 001Ch - 00FFh Reserved space for extensions
176 /* Source decimator for 2nd stereo/mono data placeholder. */
206 /* FIFO Level (FL): Current FIFO Level in the Asynchronous FIFO. */
224 #define CIC_CONTROL_MIC_A_POLARITY BIT(2)
272 #define FIR_CONTROL_AUTO_MUTE BIT(2)
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/include/ |
| D | dmic_regs.h | 1 /* SPDX-License-Identifier: Apache-2.0 */
42 /* Capture Link Select - select which link wall clock to time stamp. */
68 /* Common FIFO channels register (primary & secondary) (0000 - 0FFF)
82 * (crossed out) 0010h LOCAL_TSC0 64-bit Wall Clock timestamp
83 * (crossed out) 0018h LOCAL_SAMPLE0 64-bit Sample Count
84 * 001Ch - 00FFh Reserved space for extensions
179 /* Source decimator for 2nd stereo/mono data placeholder. */
209 /* FIFO Level (FL): Current FIFO Level in the Asynchronous FIFO. */
227 #define CIC_CONTROL_MIC_A_POLARITY BIT(2)
257 #define MIC_CONTROL_SLAVE_MODE BIT(2)
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| /Zephyr-Core-3.5.0/doc/project/ |
| D | release_process.rst | 6 The Zephyr project releases on a time-based cycle, rather than a feature-driven
10 A time-based release process enables the Zephyr project to provide users with a
12 roughly 4-month release cycle allows the project to coordinate development of
19 - Release tagging procedure:
21 - linear mode on main branch,
22 - release branches for maintenance after release tagging.
23 - Each release period will consist of a development phase followed by a
29 - Development phase: all changes are considered and merged, subject to
31 - Stabilisation phase: the release manager creates a vN-rc1 tag and the tree
33 - CI sees the tag, builds and runs tests; Test teams analyse the report from the
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| /Zephyr-Core-3.5.0/tests/kernel/mutex/sys_mutex/src/ |
| D | main.c | 2 * Copyright (c) 2012-2016 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
13 * A thread that owns a mutex is promoted to the priority level of the
14 * highest-priority thread attempting to lock the mutex.
25 * - 0.0 sec: thread_05, thread_06, thread_07, thread_08, thread_09, sleep
27 * - 0.0 sec: thread_11 sleeps
28 * - 0.5 sec: thread_09 wakes and waits on mutex_1
29 * - 1.0 sec: main thread (@ priority 9) takes mutex_2 then sleeps
30 * - 1.5 sec: thread_08 wakes and waits on mutex_2
31 * - 2.0 sec: main thread (@ priority 8) takes mutex_3 then sleeps
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| /Zephyr-Core-3.5.0/tests/net/net_pkt/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
31 if (mac_addr[2] == 0U) { in fake_dev_iface_init()
32 /* 00-00-5E-00-53-xx Documentation RFC 7042 */ in fake_dev_iface_init()
35 mac_addr[2] = 0x5E; in fake_dev_iface_init()
95 if (!pkt || !pkt->cursor.buf || !pkt->cursor.pos) { in pkt_print_cursor()
99 pkt->cursor.pos - pkt->cursor.buf->data, in pkt_print_cursor()
100 pkt->cursor.pos, pkt->cursor.buf, in pkt_print_cursor()
101 pkt->cursor.buf->data); in pkt_print_cursor()
107 * HOW TO ALLOCATE - 2 TESTS *
119 zassert_true(atomic_get(&pkt->atomic_ref) == 0, in ZTEST()
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| /Zephyr-Core-3.5.0/doc/_static/css/ |
| D | custom.css | 2 * Copyright (c) 2019-2020, Juan Linietsky, Ariel Manzur and the Godot community
4 * SPDX-License-Identifier: CC-BY-3.0
24 .rst-content .toctree-wrapper p.caption,
25 .rst-versions {
27 …font-family: system-ui, -apple-system, "Segoe UI", Roboto, "Helvetica Neue", Arial, "Noto Sans", s…
37 .rst-content .toctree-wrapper p.caption {
39 font-weight: 500;
42 .rst-content div.figure p.caption {
44 text-align: center;
45 margin-top: 8px;
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| /Zephyr-Core-3.5.0/samples/drivers/espi/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
90 SAF_ERASE_64K = 2,
140 .version = 2U, /* TODO */
175 static const struct espi_saf_pr w25q128_protect_regions[2] = {
190 .pr_num = 2U,
197 .nregions = 2U,
204 * 2. Read JEDEC ID and verify its a W25Q128
269 return -1; in spi_saf_init()
330 txb.len = 2U; in spi_saf_init()
359 /* read 2 bytes both will be STATUS1 */ in spi_saf_init()
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| /Zephyr-Core-3.5.0/drivers/modem/ |
| D | wncm14a2a.c | 4 * SPDX-License-Identifier: Apache-2.0
80 .cmd_len = (uint16_t)sizeof(cmd_)-1, \
191 while (length--) { in hexdump()
223 for (i = 0; i < (16 - (n % 16)); i++) { in hexdump()
278 sock->context = NULL; in socket_put()
279 sock->socket_id = 0; in socket_put()
280 (void)memset(&sock->src, 0, sizeof(struct sockaddr)); in socket_put()
281 (void)memset(&sock->dst, 0, sizeof(struct sockaddr)); in socket_put()
289 if (addr->sa_family == AF_INET6) { in wncm14a2a_sprint_ip_addr()
290 return net_addr_ntop(AF_INET6, &net_sin6(addr)->sin6_addr, in wncm14a2a_sprint_ip_addr()
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