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/Zephyr-Core-3.7.0/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a77961.h58 #define PIN_CLKOUT RCAR_GP_PIN(1, 28)
162 #define PIN_USB30_PWEN RCAR_GP_PIN(6, 28)
197 #define PIN_QSPI0_SPCLK RCAR_NOGP_PIN(28)
239 #define FUNC_IRQ1 IPSR(0, 28, 0)
240 #define FUNC_QPOLA IPSR(0, 28, 1)
241 #define FUNC_DU_DISP IPSR(0, 28, 3)
242 #define FUNC_VI4_DATA1_B IPSR(0, 28, 4)
243 #define FUNC_CAN0_RX_B IPSR(0, 28, 5)
244 #define FUNC_CANFD0_RX_B IPSR(0, 28, 6)
245 #define FUNC_MSIOF3_SS1_E IPSR(0, 28, 7)
[all …]
Dpinctrl-r8a77951.h57 #define PIN_CLKOUT RCAR_GP_PIN(1, 28)
161 #define PIN_USB30_PWEN RCAR_GP_PIN(6, 28)
196 #define PIN_QSPI0_SPCLK RCAR_NOGP_PIN(28)
239 #define FUNC_IRQ1 IPSR(0, 28, 0)
240 #define FUNC_QPOLA IPSR(0, 28, 1)
241 #define FUNC_DU_DISP IPSR(0, 28, 3)
242 #define FUNC_VI4_DATA1_B IPSR(0, 28, 4)
243 #define FUNC_CAN0_RX_B IPSR(0, 28, 5)
244 #define FUNC_CANFD0_RX_B IPSR(0, 28, 6)
245 #define FUNC_MSIOF3_SS1_E IPSR(0, 28, 7)
[all …]
Dpinctrl-r8a779f0.h123 #define PIN_MSPI1SC RCAR_GP_PIN(4, 28)
198 #define PIN_CAN14TX RCAR_GP_PIN(7, 28)
228 #define FUNC_TX0 IP0SR0(28, 0)
229 #define FUNC_HTX1 IP0SR0(28, 1)
230 #define FUNC_MSIOF1_TXD IP0SR0(28, 3)
231 #define FUNC_TSN1_AVTP_CAPTURE_A IP0SR0(28, 5)
257 #define FUNC_MSIOF0_SS1 IP1SR0(28, 0)
258 #define FUNC_HRTS3_N IP1SR0(28, 1)
259 #define FUNC_RTS1_N IP1SR0(28, 2)
260 #define FUNC_IRQ5 IP1SR0(28, 3)
[all …]
/Zephyr-Core-3.7.0/drivers/can/
DKconfig.stm3219 range 0 28
30 CAN_MAX_STD_ID_FILTER + CAN_MAX_EXT_ID_FILTER * 2 <= 28
46 CAN_MAX_STD_ID_FILTER + CAN_MAX_EXT_ID_FILTER * 2 <= 28
61 default 28
62 range 0 28
/Zephyr-Core-3.7.0/boards/particle/nrf52_blenano2/
Dnrf52_blenano2-pinctrl.dtsi12 <NRF_PSEL(UART_CTS, 0, 28)>;
21 <NRF_PSEL(UART_CTS, 0, 28)>;
28 psels = <NRF_PSEL(TWIM_SDA, 0, 28)>,
35 psels = <NRF_PSEL(TWIM_SDA, 0, 28)>,
/Zephyr-Core-3.7.0/boards/we/proteus2ev/
Dwe_proteus2ev_nrf52832-pinctrl.dtsi9 <NRF_PSEL(UART_CTS, 0, 28)>;
19 <NRF_PSEL(UART_CTS, 0, 28)>;
41 psels = <NRF_PSEL(SPIM_SCK, 0, 28)>,
49 psels = <NRF_PSEL(SPIM_SCK, 0, 28)>,
/Zephyr-Core-3.7.0/samples/net/sockets/dumb_http_server_mt/
Ddocker-test.sh17 # curl timeout is return code 28. If we get that, zephyr will never
19 if [ $docker_result -eq 28 ]; then
48 # curl timeout is return code 28. If we get that, zephyr will never
50 if [ $docker_result -eq 28 ]; then
/Zephyr-Core-3.7.0/tests/drivers/sensor/bmi160/src/
Dfixture.c19 {SENSOR_CHAN_ACCEL_X, 0}, {SENSOR_CHAN_ACCEL_Y, 1 << 28}, in sensor_bmi160_setup_emulator()
20 {SENSOR_CHAN_ACCEL_Z, 2 << 28}, {SENSOR_CHAN_GYRO_X, 3 << 28}, in sensor_bmi160_setup_emulator()
21 {SENSOR_CHAN_GYRO_Y, 4 << 28}, {SENSOR_CHAN_GYRO_Z, 5 << 28}, in sensor_bmi160_setup_emulator()
/Zephyr-Core-3.7.0/samples/modules/cmsis_dsp/moving_average/
Dsample.yaml45 - "Input\\[28\\]: 19 20 21 22 23 24 25 26 27 28 | Output\\[28\\]: 23.50"
46 - "Input\\[29\\]: 20 21 22 23 24 25 26 27 28 29 | Output\\[29\\]: 24.50"
47 - "Input\\[30\\]: 21 22 23 24 25 26 27 28 29 30 | Output\\[30\\]: 25.50"
48 - "Input\\[31\\]: 22 23 24 25 26 27 28 29 30 31 | Output\\[31\\]: 26.50"
/Zephyr-Core-3.7.0/drivers/pinctrl/renesas/rcar/
Dpfc_r8a77951.c14 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
25 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
36 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
47 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
58 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
69 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
80 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
91 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
102 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
113 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
[all …]
Dpfc_r8a77961.c14 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
25 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
36 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
47 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
58 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
69 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
80 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
91 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
102 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
113 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
[all …]
Dpfc_r8a779f0.c15 { RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */
26 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF0_SS1 */
46 { RCAR_GP_PIN(1, 7), 28, 3 }, /* GP1_07 */
57 { RCAR_GP_PIN(1, 15), 28, 3 }, /* MMC_SD_D2 */
68 { RCAR_GP_PIN(1, 23), 28, 3 }, /* SD_CD */
83 { RCAR_GP_PIN(2, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */
94 { RCAR_GP_PIN(2, 15), 28, 3 }, /* PCIE0_CLKREQ_N */
110 { RCAR_GP_PIN(3, 7), 28, 3 }, /* TSN2_LINK_B */
121 { RCAR_GP_PIN(3, 15), 28, 3 }, /* TSN1_AVTP_CAPTURE_B */
139 { RCAR_GP_PIN(4, 7), 28, 3 }, /* GP4_07 */
[all …]
/Zephyr-Core-3.7.0/subsys/net/lib/http/
Dhttp_huffman.c246 { 28, 2, { 0b11111111, 0b11111111, 0b11111110, 0b00100000 } },
247 { 28, 3, { 0b11111111, 0b11111111, 0b11111110, 0b00110000 } },
248 { 28, 4, { 0b11111111, 0b11111111, 0b11111110, 0b01000000 } },
249 { 28, 5, { 0b11111111, 0b11111111, 0b11111110, 0b01010000 } },
250 { 28, 6, { 0b11111111, 0b11111111, 0b11111110, 0b01100000 } },
251 { 28, 7, { 0b11111111, 0b11111111, 0b11111110, 0b01110000 } },
252 { 28, 8, { 0b11111111, 0b11111111, 0b11111110, 0b10000000 } },
253 { 28, 11, { 0b11111111, 0b11111111, 0b11111110, 0b10010000 } },
254 { 28, 12, { 0b11111111, 0b11111111, 0b11111110, 0b10100000 } },
255 { 28, 14, { 0b11111111, 0b11111111, 0b11111110, 0b10110000 } },
[all …]
/Zephyr-Core-3.7.0/boards/ti/common/
Dlaunchxl_sky13317.dtsi24 gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>, <&gpio0 29 GPIO_ACTIVE_HIGH>, \
38 pinmux = <28 IOC_PORT_GPIO>;
42 pinmux = <28 IOC_PORT_RFC_GPO0>;
/Zephyr-Core-3.7.0/samples/subsys/zbus/msg_subscriber/
DREADME.rst34 I: AL Memory allocated 28 bytes. Total allocated 28 bytes
51 I: FR Memory freed 28 bytes. Total allocated 0 bytes
56 I: AL Memory allocated 28 bytes. Total allocated 28 bytes
73 I: FR Memory freed 28 bytes. Total allocated 0 bytes
/Zephyr-Core-3.7.0/tests/net/lib/http_server/hpack/src/
Dmain.c18 { 0x1ff8, 13, }, { 0x7fffd8, 23, }, { 0xfffffe2, 28, }, { 0xfffffe3, 28, },
19 { 0xfffffe4, 28, }, { 0xfffffe5, 28, }, { 0xfffffe6, 28, }, { 0xfffffe7, 28, },
20 { 0xfffffe8, 28, }, { 0xffffea, 24, }, { 0x3ffffffc, 30, }, { 0xfffffe9, 28, },
21 { 0xfffffea, 28, }, { 0x3ffffffd, 30, }, { 0xfffffeb, 28, }, { 0xfffffec, 28, },
22 { 0xfffffed, 28, }, { 0xfffffee, 28, }, { 0xfffffef, 28, }, { 0xffffff0, 28, },
23 { 0xffffff1, 28, }, { 0xffffff2, 28, }, { 0x3ffffffe, 30, }, { 0xffffff3, 28, },
24 { 0xffffff4, 28, }, { 0xffffff5, 28, }, { 0xffffff6, 28, }, { 0xffffff7, 28, },
25 { 0xffffff8, 28, }, { 0xffffff9, 28, }, { 0xffffffa, 28, }, { 0xffffffb, 28, },
49 { 0x7fc, 11, }, { 0x3ffd, 14, }, { 0x1ffd, 13, }, { 0xffffffc, 28, },
73 { 0xffffffd, 28, }, { 0x7ffffe3, 27, }, { 0x7ffffe4, 27, }, { 0x7ffffe5, 27, },
[all …]
/Zephyr-Core-3.7.0/dts/xtensa/espressif/esp32/
Desp32_wrover_e_n8r8.dtsi11 gpio-reserved-ranges = <20 1>, <24 1>, <28 4>;
13 <20 1>, <24 1>, <28 4>; // NC
/Zephyr-Core-3.7.0/dts/bindings/dsa/
Dmicrochip,ksz8794.yaml23 Supported values 2,4,8,12,16,20,24,28mA
33 - 28
/Zephyr-Core-3.7.0/dts/bindings/gpio/
Dquicklogic,eos-s3-gpio.yaml24 "2 : 11 / 28"
30 E.g. configuring GPIO 2 as secondary results in controlling pin 28,
/Zephyr-Core-3.7.0/soc/xlnx/zynq7000/common/
Dpinctrl_soc.h18 /* MIO_PIN_xx SLCR register fields (from Xilinx UG585 v1.13, B.28 SLCR) */
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
136 #define MIO28 28
165 #define MIO_GROUP_ETHERNET1_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
176 #define MIO_GROUP_SPI0_1_GRP_PINS 28, 29, 33
201 #define MIO_GROUP_SDIO0_1_GRP_PINS 28, 29, 30, 31, 32, 33
213 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
234 #define MIO_GROUP_CAN1_5_GRP_PINS 28, 29
257 #define MIO_GROUP_UART1_5_GRP_PINS 28, 29
[all …]
/Zephyr-Core-3.7.0/soc/intel/apollo_lake/
Dsoc_gpio.h51 #define APL_GPIO_28 28
85 #define APL_GPIO_72 28
135 #define APL_GPIO_215 28
169 #define APL_GPIO_FST_SPI_CLK_FB 28
218 #define APL_GPIO_211 28
269 #define APL_GPIO_186 28
/Zephyr-Core-3.7.0/boards/96boards/carbon/
D96b_carbon_nrf51822-pinctrl.dtsi9 psels = <NRF_PSEL(TWIM_SDA, 0, 28)>,
16 psels = <NRF_PSEL(TWIM_SDA, 0, 28)>,
/Zephyr-Core-3.7.0/dts/arm64/broadcom/
Dbcm2711.dtsi69 ngpios = <28>;
73 /* GPIO 28 ~ 45 */
76 reg = <28>;
/Zephyr-Core-3.7.0/boards/ruuvi/ruuvitag/
Druuvi_ruuvitag-pinctrl.dtsi30 <NRF_PSEL(SPIM_MISO, 0, 28)>;
38 <NRF_PSEL(SPIM_MISO, 0, 28)>;
/Zephyr-Core-3.7.0/boards/ezurio/bl5340_dvk/
Dbl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi26 <NRF_PSEL(SPIM_SCK, 0, 28)>;
34 <NRF_PSEL(SPIM_SCK, 0, 28)>;
113 psels = <NRF_PSEL(PWM_OUT0, 0, 28)>;
119 psels = <NRF_PSEL(PWM_OUT0, 0, 28)>;

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