Home
last modified time | relevance | path

Searched full:22 (Results 1 – 25 of 667) sorted by relevance

12345678910>>...27

/Zephyr-Core-3.5.0/tests/kernel/common/src/
Dprintk.c28 char expected_32[] = "22 113 10000 32768 40000 22\n"
29 "p 112 -10000 -32768 -40000 -22\n"
44 char expected_64[] = "22 113 10000 32768 40000 22\n"
45 "p 112 -10000 -32768 -40000 -22\n"
59 char *expected = "22 113 10000 32768 40000 22\n"
60 "p 112 -10000 -32768 -40000 -22\n"
72 char *expected = "22 113 10000 32768 40000 %llu\n"
85 char *expected = "22 113 10000 32768 40000 22\n"
86 "p 112 -10000 -32768 -40000 -22\n"
100 size_t stv = 22;
[all …]
/Zephyr-Core-3.5.0/samples/bluetooth/broadcaster_multiple/
Dprj.conf11 # - 31 bytes will use 22 bytes for the default name in this sample plus 9 bytes
13 # - 191 bytes will use 22 bytes for the default name in this sample plus 169
15 # - 277 bytes will use 22 bytes for the default name in this sample plus 255
/Zephyr-Core-3.5.0/tests/bsim/bluetooth/host/adv/chain/
Dprj.conf14 # - 31 bytes will use 22 bytes for the default name in this sample plus 9 bytes
16 # - 191 bytes will use 22 bytes for the default name in this sample plus 169
18 # - 277 bytes will use 22 bytes for the default name in this sample plus 255
/Zephyr-Core-3.5.0/dts/bindings/lora/
Dst,stm32wl-subghz-radio.yaml43 default: 22
47 The default setting of +22 dBm is a prevalent board configuration;
56 - 22
/Zephyr-Core-3.5.0/samples/net/cloud/aws_iot_mqtt/
DREADME.rst90 7b 22 63 6f 75 6e 74 65 72 22 3a 30 7d |{"counte r":0}
94 7b 0a 20 20 22 6d 65 73 73 61 67 65 22 3a 20 22 |{. "mes sage": "
96 6f 54 20 63 6f 6e 73 6f 6c 65 22 0a 7d |oT conso le".}
99 7b 22 63 6f 75 6e 74 65 72 22 3a 31 7d |{"counte r":1}
/Zephyr-Core-3.5.0/samples/userspace/shared_mem/src/
Dmain.h54 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25}
56 17, 18, 19, 20, 21, 22, 23, 24, 25, 5, 0, 4, 1, 3, 2}
58 15, 14, 17, 16, 19, 18, 21, 20, 23, 22, 25, 24}
/Zephyr-Core-3.5.0/tests/drivers/adc/adc_api/boards/
Dmr_canhubk3.overlay11 io-channels = <&adc0 22>, <&adc0 23>;
22 reg = <22>;
/Zephyr-Core-3.5.0/soc/x86/apollo_lake/
Dsoc_gpio.h45 #define APL_GPIO_22 22
79 #define APL_GPIO_66 22
129 #define APL_GPIO_PMC_SPI_TXC 22
163 #define APL_GPIO_98 22
212 #define APL_GPIO_152 22
263 #define APL_GPIO_173 22
/Zephyr-Core-3.5.0/soc/riscv/riscv-ite/it8xxx2/
Dilm.c201 SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22),
202 SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22),
/Zephyr-Core-3.5.0/boards/arm/nrf9160dk_nrf52840/dts/
Dnrf9160dk_uart1_on_if0_3.dtsi21 <NRF_PSEL(UART_CTS, 0, 22)>;
30 <NRF_PSEL(UART_CTS, 0, 22)>;
/Zephyr-Core-3.5.0/drivers/lora/
Dsx126x_stm32wl.c94 power = 22 - (max_power - power); in sx126x_set_tx_params()
97 power = 22 - (max_power - power); in sx126x_set_tx_params()
101 } else { /* default +22 dBm */ in sx126x_set_tx_params()
103 power = 22 - (max_power - power); in sx126x_set_tx_params()
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/clock/
Dgd32l23x-clocks.h38 #define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHB1EN, 22U)
59 #define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U)
74 #define GD32_CLOCK_DBGMCU GD32_CLOCK_CONFIG(APB2EN, 22U)
Dstm32f410_clock.h18 #define SAI1B_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR_REG)
24 #define I2CFMP1_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR2_REG)
/Zephyr-Core-3.5.0/samples/tfm_integration/psa_crypto/src/
Dpsa_attestation.c101 * 00 11 22 33 44 55 66 77 88 99 AA BB CC DD EE FF in att_test()
102 * 00 11 22 33 44 55 66 77 88 99 AA BB CC DD EE FF in att_test()
103 * 00 11 22 33 44 55 66 77 88 99 AA BB CC DD EE FF in att_test()
104 * 00 11 22 33 44 55 66 77 88 99 AA BB CC DD EE FF in att_test()
/Zephyr-Core-3.5.0/boards/arm/degu_evk/
Ddegu_evk-pinctrl.dtsi29 <NRF_PSEL(TWIM_SCL, 0, 22)>;
36 <NRF_PSEL(TWIM_SCL, 0, 22)>;
/Zephyr-Core-3.5.0/boards/arm/96b_nitrogen/
D96b_nitrogen-pinctrl.dtsi29 <NRF_PSEL(TWIM_SCL, 0, 22)>;
36 <NRF_PSEL(TWIM_SCL, 0, 22)>;
/Zephyr-Core-3.5.0/boards/arm/blueclover_plt_demo_v2_nrf52832/
Dblueclover_plt_demo_v2_nrf52832-pinctrl.dtsi39 psels = <NRF_PSEL(PWM_OUT0, 0, 22)>;
46 psels = <NRF_PSEL(PWM_OUT0, 0, 22)>;
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/
Dsoc_pins.h37 #define MCHP_GPIO_026 (22U)
71 #define MCHP_GPIO_066 (22U)
105 #define MCHP_GPIO_126 (22U)
139 #define MCHP_GPIO_166 (22U)
173 #define MCHP_GPIO_226 (22U)
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/
Drpi-pico-rp2040-pinctrl.h53 #define UART1_CTS_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_UART)
84 #define I2C1_SDA_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_I2C)
115 #define PWM_3A_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PWM)
146 #define SPI0_SCK_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_SPI)
182 #define PIO0_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PIO0)
213 #define PIO1_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PIO1)
/Zephyr-Core-3.5.0/boards/arm/nrf52832_mdk/
Dnrf52832_mdk-pinctrl.dtsi58 psels = <NRF_PSEL(PWM_OUT0, 0, 22)>,
67 psels = <NRF_PSEL(PWM_OUT0, 0, 22)>,
/Zephyr-Core-3.5.0/boards/riscv/rv32m1_vega/
Drv32m1_vega-pinctrl.dtsi55 <RV32M1_MUX('B', 22, 2)>,
63 pinmux = <RV32M1_MUX('A', 22, 6)>,
/Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/common/
Dpinctrl_soc.h130 #define MIO22 22
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
188 #define MIO_GROUP_SPI1_1_GRP_PINS 22, 23, 24
204 #define MIO_GROUP_SDIO1_1_GRP_PINS 22, 23, 24, 25, 26, 27
212 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
217 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23
221 #define MIO_GROUP_CAN0_3_GRP_PINS 22, 23
244 #define MIO_GROUP_UART0_3_GRP_PINS 22, 23
267 #define MIO_GROUP_I2C0_3_GRP_PINS 22, 23
319 #define MIO_GROUP_GPIO0_22_GRP_PINS 22
/Zephyr-Core-3.5.0/dts/bindings/mtd/
Dnxp,imx-flexspi-hyperflash.yaml1 # Copyright 2020-22 NXP
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/reg/
Dmec172x_ecia.h23 #define MCHP_ECIA_GIRQ_CLK_WAKE_ONLY 22u
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
171 #define MCHP_GPIO_0166_GIRQ_POS 22
199 #define MCHP_GPIO_0166_GIRQ_BIT BIT(22)
231 #define MCHP_GPIO_0126_GIRQ_POS 22
262 #define MCHP_GPIO_0126_GIRQ_BIT BIT(22)
295 #define MCHP_GPIO_0066_GIRQ_POS 22
327 #define MCHP_GPIO_0066_GIRQ_BIT BIT(22)
361 #define MCHP_GPIO_0026_GIRQ_POS 22
393 #define MCHP_GPIO_0026_GIRQ_BIT BIT(22)
[all …]
/Zephyr-Core-3.5.0/boards/arm/rm1xx_dvk/
Drm1xx_dvk-pinctrl.dtsi59 <NRF_PSEL(UART_RX, 0, 22)>,
68 <NRF_PSEL(UART_RX, 0, 22)>,

12345678910>>...27