| /Zephyr-Core-3.6.0/boards/arm/reel_board/ |
| D | reel_board_v2-pinctrl.dtsi | 11 <NRF_PSEL(SPIM_MISO, 0, 21)>;
19 <NRF_PSEL(SPIM_MISO, 0, 21)>;
|
| D | reel_board-pinctrl.dtsi | 11 <NRF_PSEL(SPIM_MISO, 0, 21)>;
19 <NRF_PSEL(SPIM_MISO, 0, 21)>;
|
| /Zephyr-Core-3.6.0/dts/bindings/sensor/ |
| D | st,stm32-temp.yaml | 18 STM32F4 Table 6.3.21 default 2.5
27 STM32F4 Table 6.3.21 default 760
|
| /Zephyr-Core-3.6.0/boards/arm/nrf9160dk_nrf9160/dts/ |
| D | nrf9160dk_uart1_on_if0_3.dtsi | 12 <NRF_PSEL(UART_RTS, 0, 21)>,
21 <NRF_PSEL(UART_RTS, 0, 21)>,
|
| /Zephyr-Core-3.6.0/samples/userspace/shared_mem/src/ |
| D | main.h | 54 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25}
56 17, 18, 19, 20, 21, 22, 23, 24, 25, 5, 0, 4, 1, 3, 2}
58 15, 14, 17, 16, 19, 18, 21, 20, 23, 22, 25, 24}
|
| /Zephyr-Core-3.6.0/boards/arm/xiao_ble/ |
| D | xiao_ble-pinctrl.dtsi | 88 psels = <NRF_PSEL(SPIM_SCK, 0, 21)>,
96 psels = <NRF_PSEL(SPIM_SCK, 0, 21)>,
105 psels = <NRF_PSEL(QSPI_SCK, 0, 21)>,
116 psels = <NRF_PSEL(QSPI_SCK, 0, 21)>,
|
| /Zephyr-Core-3.6.0/boards/arm/ubx_bmd380eval_nrf52840/ |
| D | ubx_bmd380eval_nrf52840-pinctrl.dtsi | 93 <NRF_PSEL(SPIM_MISO, 0, 21)>;
101 <NRF_PSEL(SPIM_MISO, 0, 21)>;
110 <NRF_PSEL(QSPI_IO1, 0, 21)>,
121 <NRF_PSEL(QSPI_IO1, 0, 21)>,
|
| /Zephyr-Core-3.6.0/include/zephyr/dt-bindings/pinctrl/ |
| D | esp32c3-pinctrl.h | 77 ESP32_PINMUX(21, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
144 ESP32_PINMUX(21, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
211 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
278 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
345 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
412 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
479 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
546 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
613 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS0_OUT)
680 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS1_OUT)
[all …]
|
| D | rpi-pico-rp2040-pinctrl.h | 52 #define UART1_RX_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_UART)
83 #define I2C0_SCL_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_I2C)
114 #define PWM_2B_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PWM)
145 #define SPI0_CSN_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_SPI)
181 #define PIO0_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PIO0)
212 #define PIO1_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PIO1)
224 #define GPOUT0_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_GPCK)
|
| /Zephyr-Core-3.6.0/soc/x86/apollo_lake/ |
| D | soc_gpio.h | 44 #define APL_GPIO_21 21
78 #define APL_GPIO_65 21
128 #define APL_GPIO_PMC_SPI_RXD 21
162 #define APL_GPIO_97 21
211 #define APL_GPIO_151 21
262 #define APL_GPIO_179 21
|
| /Zephyr-Core-3.6.0/soc/riscv/ite_ec/it8xxx2/ |
| D | ilm.c | 198 SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21),
199 SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21),
|
| /Zephyr-Core-3.6.0/dts/arm/microchip/ |
| D | mec172x_common.dtsi | 30 direct-capable-girqs = <13 14 15 16 17 18 19 20 21 23>;
44 16 17 18 21 22 24 25
55 16 17 18 19 20 21 22 23
66 16 17 18 19 20 21 22 23
77 16 17 18 19 20 21 22 23
88 16 17 18 19 20 21 22 23
133 16 17 20 21 22 23>;
142 10 20 21 22 23
194 20 21 22 23 24 25 26 27>;
286 girqs = <21 2>;
[all …]
|
| /Zephyr-Core-3.6.0/include/zephyr/dt-bindings/reset/ |
| D | gd32a50x.h | 41 #define GD32_RESET_GPIOE GD32_RESET_CONFIG(AHBRST, 21U)
52 #define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U)
68 #define GD32_RESET_TIMER20 GD32_RESET_CONFIG(APB2RST, 21U)
|
| /Zephyr-Core-3.6.0/include/zephyr/dt-bindings/clock/ |
| D | gd32a50x-clocks.h | 40 #define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(AHBEN, 21U)
51 #define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U)
67 #define GD32_CLOCK_TIMER20 GD32_CLOCK_CONFIG(APB2EN, 21U)
|
| /Zephyr-Core-3.6.0/dts/bindings/gpio/ |
| D | arduino-nano-header-r3.yaml | 16 through 13 correspond to D0 through D13, and parent pins 14 through 21
23 2 D2 A7/D21 21
|
| D | particle-gen3-header.yaml | 18 from the bottom; and pins 9 through 21 correspond to pins on the
23 21 RESETn
|
| D | ti,boosterpack-header.yaml | 14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
17 1 3.3V 21 5V 40 GPIO 20 GND
|
| D | arduino-header-r3.yaml | 24 through 5 correspond to A0 through A5, and parent pins 6 through 21
27 D15 21
|
| D | arduino-mkr-header.yaml | 18 through 14 correspond to D0 through D21, and parent pins 15 through 21
28 21 A6/D21 D12/SCL 12
|
| /Zephyr-Core-3.6.0/boards/arm/particle_argon/dts/ |
| D | mesh_feather-pinctrl.dtsi | 26 <NRF_PSEL(SPIM_MISO, 0, 21)>;
34 <NRF_PSEL(SPIM_MISO, 0, 21)>;
|
| /Zephyr-Core-3.6.0/boards/arm/particle_xenon/dts/ |
| D | mesh_feather-pinctrl.dtsi | 26 <NRF_PSEL(SPIM_MISO, 0, 21)>;
34 <NRF_PSEL(SPIM_MISO, 0, 21)>;
|
| /Zephyr-Core-3.6.0/boards/arm/particle_boron/dts/ |
| D | mesh_feather-pinctrl.dtsi | 26 <NRF_PSEL(SPIM_MISO, 0, 21)>;
34 <NRF_PSEL(SPIM_MISO, 0, 21)>;
|
| /Zephyr-Core-3.6.0/soc/arm/xilinx_zynq7000/common/ |
| D | pinctrl_soc.h | 89 #define MIO_PIN_SPECIAL_MASK_SDIO0_CD GENMASK(21, 16)
99 #define MIO_PIN_SPECIAL_MASK_SDIO1_CD GENMASK(21, 16)
129 #define MIO21 21
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
172 #define MIO_GROUP_SPI0_0_GRP_PINS 16, 17, 21
200 #define MIO_GROUP_SDIO0_0_GRP_PINS 16, 17, 18, 19, 20, 21
212 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
217 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23
232 #define MIO_GROUP_CAN1_3_GRP_PINS 20, 21
255 #define MIO_GROUP_UART1_3_GRP_PINS 20, 21
[all …]
|
| /Zephyr-Core-3.6.0/boards/arm/degu_evk/ |
| D | degu_evk-pinctrl.dtsi | 12 <NRF_PSEL(UART_CTS, 0, 21)>;
21 <NRF_PSEL(UART_CTS, 0, 21)>;
|
| /Zephyr-Core-3.6.0/boards/arm/ubx_bmd345eval_nrf52840/ |
| D | ubx_bmd345eval_nrf52840-pinctrl.dtsi | 108 <NRF_PSEL(SPIM_MISO, 0, 21)>;
116 <NRF_PSEL(SPIM_MISO, 0, 21)>;
142 <NRF_PSEL(QSPI_IO1, 0, 21)>,
153 <NRF_PSEL(QSPI_IO1, 0, 21)>,
|
