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/Zephyr-latest/samples/modules/cmsis_dsp/moving_average/
Dsample.yaml7 - samples
9 - qemu_cortex_m0
10 - native_sim
12 - cmsis-dsp
17 - "Input\\[00\\]: 0 0 0 0 0 0 0 0 0 0 | Output\\[00\\]: 0.00"
18 - "Input\\[01\\]: 0 0 0 0 0 0 0 0 0 1 | Output\\[01\\]: 0.10"
19 - "Input\\[02\\]: 0 0 0 0 0 0 0 0 1 2 | Output\\[02\\]: 0.30"
20 - "Input\\[03\\]: 0 0 0 0 0 0 0 1 2 3 | Output\\[03\\]: 0.60"
21 - "Input\\[04\\]: 0 0 0 0 0 0 1 2 3 4 | Output\\[04\\]: 1.00"
22 - "Input\\[05\\]: 0 0 0 0 0 1 2 3 4 5 | Output\\[05\\]: 1.50"
[all …]
/Zephyr-latest/samples/userspace/shared_mem/src/
Dmain.h4 * SPDX-License-Identifier: Apache-2.0
54 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25}
56 17, 18, 19, 20, 21, 22, 23, 24, 25, 5, 0, 4, 1, 3, 2}
58 15, 14, 17, 16, 19, 18, 21, 20, 23, 22, 25, 24}
/Zephyr-latest/soc/intel/apollo_lake/
Dsoc_gpio.h2 * Copyright (c) 2018-2019, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
44 #define APL_GPIO_21 21
46 #define APL_GPIO_23 23
78 #define APL_GPIO_65 21
80 #define APL_GPIO_67 23
128 #define APL_GPIO_PMC_SPI_RXD 21
130 #define APL_GPIO_PMC_SPI_CLK 23
162 #define APL_GPIO_97 21
164 #define APL_GPIO_99 23
[all …]
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dilm.c4 * SPDX-License-Identifier: Apache-2.0
20 * IT8xxx2 allows 4-kilobyte blocks of RAM be configured individually as either Instruction- or
32 * address range non-cacheable (which is appropriate because Flash has high latency but RAM is
42 BUILD_ASSERT((ILM_BLOCK_SIZE & (ILM_BLOCK_SIZE - 1)) == 0, "ILM_BLOCK_SIZE must be a power of two");
53 * SCAR registers contain 20-bit addresses in three registers, with one set
76 return ((uintptr_t)p & (ILM_BLOCK_SIZE - 1)) == 0; in is_block_aligned()
83 return -EFAULT; /* Not in RAM */ in it8xxx2_configure_ilm_block()
85 const int dirmap_index = ((uintptr_t)ram_addr - RAM_BASE) / ILM_BLOCK_SIZE; in it8xxx2_configure_ilm_block()
87 if (dirmap_index >= ARRAY_SIZE(config->scar_regs)) { in it8xxx2_configure_ilm_block()
88 return -EFAULT; /* Past the end of RAM */ in it8xxx2_configure_ilm_block()
[all …]
/Zephyr-latest/tests/net/lib/http_server/hpack/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
16 /* Copy-paste from RFC7541. */
18 { 0x1ff8, 13, }, { 0x7fffd8, 23, }, { 0xfffffe2, 28, }, { 0xfffffe3, 28, },
51 { 0x3fffd3, 22, }, { 0x3fffd4, 22, }, { 0x3fffd5, 22, }, { 0x7fffd9, 23, },
52 { 0x3fffd6, 22, }, { 0x7fffda, 23, }, { 0x7fffdb, 23, }, { 0x7fffdc, 23, },
53 { 0x7fffdd, 23, }, { 0x7fffde, 23, }, { 0xffffeb, 24, }, { 0x7fffdf, 23, },
54 { 0xffffec, 24, }, { 0xffffed, 24, }, { 0x3fffd7, 22, }, { 0x7fffe0, 23, },
55 { 0xffffee, 24, }, { 0x7fffe1, 23, }, { 0x7fffe2, 23, }, { 0x7fffe3, 23, },
56 { 0x7fffe4, 23, }, { 0x1fffdc, 21, }, { 0x3fffd8, 22, }, { 0x7fffe5, 23, },
57 { 0x3fffd9, 22, }, { 0x7fffe6, 23, }, { 0x7fffe7, 23, }, { 0xffffef, 24, },
[all …]
/Zephyr-latest/dts/arm/microchip/
Dmec172x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "microchip,xec-pcr";
13 reg-names = "pcrr", "vbatr";
15 core-clock-div = <1>;
17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
19 clk32kmon-period-min = <1435>;
20 clk32kmon-period-max = <1495>;
21 clk32kmon-duty-cycle-var-max = <132>;
22 clk32kmon-valid-min = <4>;
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Desp32c6-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
77 ESP32_PINMUX(21, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
83 ESP32_PINMUX(23, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
150 ESP32_PINMUX(21, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
156 ESP32_PINMUX(23, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
201 #define LEDC_CH0_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
205 #define LEDC_CH0_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
250 #define LEDC_CH1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
254 #define LEDC_CH1_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
299 #define LEDC_CH2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
[all …]
Drpi-pico-rp2350-pinctrl-common.h4 * SPDX-License-Identifier: Apache-2.0
18 #include "rpi-pico-pinctrl-common.h"
41 #define PIO2_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PIO2)
43 #define PIO2_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PIO2)
53 #define GPOUT0_P13 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_GPCK)
54 #define GPOUT1_P15 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_GPCK)
67 #define UART1_RX_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_UART_ALT)
Drpi-pico-pinctrl-common.h5 * SPDX-License-Identifier: Apache-2.0
24 /* These function are common. SoC-specific functions are defined in their
58 #define SPI0_CSN_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_SPI)
60 #define SPI0_TX_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_SPI)
89 #define UART1_RX_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_UART)
91 #define UART1_RTS_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_UART)
120 #define I2C0_SCL_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_I2C)
122 #define I2C1_SCL_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_I2C)
151 #define PWM_2B_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PWM)
153 #define PWM_3B_P22 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PWM)
[all …]
/Zephyr-latest/boards/atmarktechno/degu_evk/
Ddegu_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
11 <NRF_PSEL(UART_RTS, 0, 23)>,
12 <NRF_PSEL(UART_CTS, 0, 21)>;
20 <NRF_PSEL(UART_RTS, 0, 23)>,
21 <NRF_PSEL(UART_CTS, 0, 21)>;
22 low-power-enable;
37 low-power-enable;
52 low-power-enable;
/Zephyr-latest/soc/xlnx/zynq7000/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
89 #define MIO_PIN_SPECIAL_MASK_SDIO0_CD GENMASK(21, 16)
99 #define MIO_PIN_SPECIAL_MASK_SDIO1_CD GENMASK(21, 16)
129 #define MIO21 21
131 #define MIO23 23
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
172 #define MIO_GROUP_SPI0_0_GRP_PINS 16, 17, 21
188 #define MIO_GROUP_SPI1_1_GRP_PINS 22, 23, 24
200 #define MIO_GROUP_SDIO0_0_GRP_PINS 16, 17, 18, 19, 20, 21
[all …]
/Zephyr-latest/soc/microchip/mec/common/
Dsoc_pins.h4 * SPDX-License-Identifier: Apache-2.0
36 #define MCHP_GPIO_025 (21U)
38 #define MCHP_GPIO_027 (23U)
70 #define MCHP_GPIO_065 (21U)
72 #define MCHP_GPIO_067 (23U)
104 #define MCHP_GPIO_125 (21U)
106 #define MCHP_GPIO_127 (23U)
138 #define MCHP_GPIO_165 (21U)
140 #define MCHP_GPIO_167 (23U)
172 #define MCHP_GPIO_225 (21U)
[all …]
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v2.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
43 #define SSCR0_NCS BIT(21)
45 #define SSCR0_TIM BIT(23)
46 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
59 #define SSCR1_TFT(x) DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1)
61 #define SSCR1_RFT(x) DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1)
68 #define SSCR1_TSRE BIT(21)
70 #define SSCR1_RWOT BIT(23)
89 #define SSCR2_ACIOLBS BIT(21)
[all …]
Dssp_regs_v3.h4 * SPDX-License-Identifier: Apache-2.0
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
50 #define SSCR0_RSVD2 BIT(21)
52 #define SSCR0_TIM BIT(23)
53 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
69 #define SSCR1_RSVD21 DAI_INTEL_SSP_MASK(21, 20)
71 #define SSCR1_RWOT BIT(23)
88 #define SSCR2_ACIOLBS BIT(21)
93 #define SSSR_TUR BIT(21)
101 #define SSPSP_SFRMWDTH(x) DAI_INTEL_SSP_SET_BITS(21, 16, x)
[all …]
Dssp_regs_v1.h4 * SPDX-License-Identifier: Apache-2.0
30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
42 #define SSCR0_NCS BIT(21)
44 #define SSCR0_TIM BIT(23)
45 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
58 #define SSCR1_TFT(x) DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1)
60 #define SSCR1_RFT(x) DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1)
67 #define SSCR1_TSRE BIT(21)
69 #define SSCR1_RWOT BIT(23)
88 #define SSCR2_ACIOLBS BIT(21)
[all …]
/Zephyr-latest/subsys/net/lib/http/
Dhttp_huffman.c4 * SPDX-License-Identifier: Apache-2.0
128 { 21, 153, { 0b11111111, 0b11111110, 0b11100000, 0b00000000 } },
129 { 21, 161, { 0b11111111, 0b11111110, 0b11101000, 0b00000000 } },
130 { 21, 167, { 0b11111111, 0b11111110, 0b11110000, 0b00000000 } },
131 { 21, 172, { 0b11111111, 0b11111110, 0b11111000, 0b00000000 } },
132 { 21, 176, { 0b11111111, 0b11111111, 0b00000000, 0b00000000 } },
133 { 21, 177, { 0b11111111, 0b11111111, 0b00001000, 0b00000000 } },
134 { 21, 179, { 0b11111111, 0b11111111, 0b00010000, 0b00000000 } },
135 { 21, 209, { 0b11111111, 0b11111111, 0b00011000, 0b00000000 } },
136 { 21, 216, { 0b11111111, 0b11111111, 0b00100000, 0b00000000 } },
[all …]
/Zephyr-latest/boards/contextualelectronics/abc/
Dcontextualelectronics_abc-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
18 low-power-enable;
37 low-power-enable;
52 low-power-enable;
59 <NRF_PSEL(SPIM_MOSI, 0, 23)>,
60 <NRF_PSEL(SPIM_MISO, 0, 21)>;
67 <NRF_PSEL(SPIM_MOSI, 0, 23)>,
68 <NRF_PSEL(SPIM_MISO, 0, 21)>;
69 low-power-enable;
/Zephyr-latest/boards/u-blox/ubx_bmd380eval/
Dubx_bmd380eval_nrf52840-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
22 low-power-enable;
37 low-power-enable;
51 low-power-enable;
68 low-power-enable;
85 low-power-enable;
93 <NRF_PSEL(SPIM_MISO, 0, 21)>;
101 <NRF_PSEL(SPIM_MISO, 0, 21)>;
102 low-power-enable;
110 <NRF_PSEL(QSPI_IO1, 0, 21)>,
[all …]
/Zephyr-latest/boards/adafruit/feather_nrf52840/
Dadafruit_feather_nrf52840-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
18 low-power-enable;
33 low-power-enable;
50 low-power-enable;
59 <NRF_PSEL(QSPI_IO2, 0, 23)>,
60 <NRF_PSEL(QSPI_IO3, 0, 21)>,
70 <NRF_PSEL(QSPI_IO2, 0, 23)>,
71 <NRF_PSEL(QSPI_IO3, 0, 21)>,
73 low-power-enable;
/Zephyr-latest/boards/ezurio/rm1xx_dvk/
Drm1xx_dvk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
18 low-power-enable;
35 low-power-enable;
52 low-power-enable;
58 psels = <NRF_PSEL(UART_TX, 0, 21)>,
60 <NRF_PSEL(UART_RTS, 0, 23)>,
67 psels = <NRF_PSEL(UART_TX, 0, 21)>,
69 <NRF_PSEL(UART_RTS, 0, 23)>,
71 low-power-enable;
/Zephyr-latest/boards/arduino/mkrzero/
Darduino_mkr_connector.dtsi3 * SPDX-License-Identifier: Apache-2.0
8 compatible = "arduino-mkr-header";
9 #gpio-cells = <2>;
10 gpio-map-mask = <0xffffffff 0xffffffc0>;
11 gpio-map-pass-thru = <0 0x3f>;
12 gpio-map = <0 0 &porta 22 0>, /* D0 */
13 <1 0 &porta 23 0>, /* D1 */
19 <7 0 &porta 21 0>, /* D7 */
20 <8 0 &porta 16 0>, /* D8 / SPI-COPI */
21 <9 0 &porta 17 0>, /* D9 / SPI-SCK */
[all …]
/Zephyr-latest/boards/actinius/icarus/
Dactinius_icarus_common-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
10 <NRF_PSEL(UART_RX, 0, 23)>;
17 <NRF_PSEL(UART_RX, 0, 23)>;
18 low-power-enable;
33 low-power-enable;
48 low-power-enable;
55 <NRF_PSEL(SPIM_MOSI, 0, 21)>,
63 <NRF_PSEL(SPIM_MOSI, 0, 21)>,
65 low-power-enable;
83 low-power-enable;
/Zephyr-latest/boards/m5stack/m5stack_core2/
Dm5stack_mbus_connectors.dtsi3 * SPDX-License-Identifier: Apache-2.0
8 compatible = "m5stack,mbus-header";
9 #gpio-cells = <2>;
10 gpio-map-mask = <0xffffffff 0xffffffc0>;
11 gpio-map-pass-thru = <0 0x3f>;
12 gpio-map = /* 0 GND */
18 <6 0 &gpio0 23 0>, /* MOSI */
28 <16 0 &gpio0 21 0>, /* intSDA */
33 <21 0 &gpio0 19 0>, /* GPIO */
35 <23 0 &gpio0 0 0>, /* GPIO */
/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dnpcx7_reset.h4 * SPDX-License-Identifier: Apache-2.0
34 #define NPCX_RESET_ITIM16_4 (NPCX_RESET_SWRST_CTL1_OFFSET + 21)
36 #define NPCX_RESET_ITIM16_6 (NPCX_RESET_SWRST_CTL1_OFFSET + 23)
64 #define NPCX_RESET_PWM5 (NPCX_RESET_SWRST_CTL2_OFFSET + 21)
66 #define NPCX_RESET_PWM7 (NPCX_RESET_SWRST_CTL2_OFFSET + 23)
88 #define NPCX_RESET_SYSCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 23)
/Zephyr-latest/boards/seeed/xiao_ble/
Dxiao_ble-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
13 bias-pull-up;
21 low-power-enable;
36 low-power-enable;
51 low-power-enable;
66 low-power-enable;
80 low-power-enable;
97 low-power-enable;
103 psels = <NRF_PSEL(SPIM_SCK, 0, 21)>,
111 psels = <NRF_PSEL(SPIM_SCK, 0, 21)>,
[all …]

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