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/Zephyr-Core-3.5.0/dts/bindings/clock/
Dnuvoton,npcx-pcc.yaml14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
35 120000000, 120 MHz
36 100000000, 100 MHz
37 96000000, 96 MHz
38 90000000, 90 MHz
39 80000000, 80 MHz
[all …]
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/ethernet/
Dxlnx_gem.h28 #define XLNX_GEM_MDC_DIVIDER_8 0 /* cpu_1x or IOU_SWITCH_CLK < 20 MHz */
29 #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */
30 #define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or IOU_SWITCH_CLK 40 - 80 MHz */
31 #define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x or IOU_SWITCH_CLK 80 - 120 MHz */
32 #define XLNX_GEM_MDC_DIVIDER_64 4 /* cpu_1x or IOU_SWITCH_CLK 120 - 160 MHz */
33 #define XLNX_GEM_MDC_DIVIDER_96 5 /* cpu_1x or IOU_SWITCH_CLK 160 - 240 MHz */
34 #define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x or IOU_SWITCH_CLK 240 - 320 MHz */
35 #define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x or IOU_SWITCH_CLK 320 - 540 MHz */
/Zephyr-Core-3.5.0/subsys/lorawan/
DKconfig25 default 20
38 bool "Asia 923MHz Frequency band"
41 bool "Australia 915MHz Frequency band"
44 bool "China 470MHz Frequency band"
47 bool "China 779MHz Frequency band"
50 bool "Europe 433MHz Frequency band"
53 bool "Europe 868MHz Frequency band"
56 bool "South Korea 920MHz Frequency band"
59 bool "India 865MHz Frequency band"
62 bool "North America 915MHz Frequency band"
[all …]
/Zephyr-Core-3.5.0/boards/shields/mikroe_eth_click/boards/
Dlpcxpresso55s69_cpu0.overlay12 cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>,
23 /* Errata B7/1 specifies min 8Mhz, 20MHz max according to RM */
Dlpcxpresso55s69_ns.overlay12 cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>,
23 /* Errata B7/1 specifies min 8Mhz, 20MHz max according to RM */
/Zephyr-Core-3.5.0/drivers/spi/
Dspi_esp32_spim.h17 #define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) /* 8.89MHz */
18 #define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) /* 10MHz */
19 #define SPI_MASTER_FREQ_11M (APB_CLK_FREQ/7) /* 11.43MHz */
20 #define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/6) /* 13.33MHz */
21 #define SPI_MASTER_FREQ_16M (APB_CLK_FREQ/5) /* 16MHz */
22 #define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/4) /* 20MHz */
23 #define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) /* 26.67MHz */
24 #define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) /* 40MHz */
25 #define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) /* 80MHz */
/Zephyr-Core-3.5.0/tests/benchmarks/latency_measure/
Dtestcase.yaml25 # is achievable only if frequency is below 0x00FFFFFF (around 16MHz)
26 # 20 Ticks per secondes allows a frequency up to 335544300Hz (335MHz)
31 - CONFIG_SYS_CLOCK_TICKS_PER_SEC=20
/Zephyr-Core-3.5.0/drivers/modem/
DKconfig.hl780079 bool "Band 1 (2000MHz)"
82 Enable Band 1 (2000MHz)
85 bool "Band 2 (1900MHz)"
88 Enable Band 2 (1900MHz)
91 bool "Band 3 (1800MHz)"
94 Enable Band 3 (1800MHz)
97 bool "Band 4 (1700MHz)"
100 Enable Band 4 (1700MHz)
103 bool "Band 5 (850MHz)"
106 Enable Band 5 (850MHz)
[all …]
/Zephyr-Core-3.5.0/samples/boards/ti/cc13x2_cc26x2/system_off/src/
Dext_flash.c18 #define DIO20_PIN 20
42 * 3 cycles per loop: 8 loops @ 48 Mhz = 0.5 us. in CC1352R1_LAUNCHXL_sendExtFlashByte()
52 * 3 cycles per loop: 700 loops @ 48 Mhz ~= 44 us in CC1352R1_LAUNCHXL_sendExtFlashByte()
64 * least 20 ns and ten wait at least 35 us. in CC1352R1_LAUNCHXL_wakeUpExtFlash()
67 /* Toggle chip select for ~20ns to wake ext. flash */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
69 /* 3 cycles per loop: 1 loop @ 48 Mhz ~= 62 ns */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
72 /* 3 cycles per loop: 560 loops @ 48 Mhz ~= 35 us */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
/Zephyr-Core-3.5.0/boards/shields/mikroe_eth_click/
Dmikroe_eth_click.overlay13 /* Errata B7/1 specifies min 8Mhz, 20MHz max according to RM */
/Zephyr-Core-3.5.0/soc/arm/nuvoton_npcx/
DKconfig56 bool "SPI flash max clock rate of 20 MHz"
59 bool "SPI flash max clock rate of 25 MHz"
62 bool "SPI flash max clock rate of 33 MHz"
66 bool "SPI flash max clock rate of 40 MHz"
69 bool "SPI flash max clock rate of 50 MHz"
74 default 20 if NPCX_HEADER_SPI_MAX_CLOCK_20
/Zephyr-Core-3.5.0/tests/drivers/flash/common/boards/
Dnrf52840dk_spi_nor.overlay48 spi-max-frequency = <8000000>; // chip supports 80Mhz, SPI0 supports 8MHz
55 e5 20 f1 ff ff ff ff 00 44 eb 08 6b 08 3b 04 bb
56 ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
Dnrf52840dk_spi_nor_wp_hold.overlay48 spi-max-frequency = <8000000>; // chip supports 80Mhz, SPI0 supports 8MHz
57 e5 20 f1 ff ff ff ff 00 44 eb 08 6b 08 3b 04 bb
58 ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
/Zephyr-Core-3.5.0/boards/arm/stm32g081b_eval/
Dstm32g081b_eval.dts164 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
167 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
168 * range is 9 <--> 18 MHz.
170 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
177 * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
178 * 2. tTransitionWindow - 12 to 20 uSec
195 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
198 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
199 * range is 9 <--> 18 MHz.
201 * +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
[all …]
/Zephyr-Core-3.5.0/soc/arm/arm/beetle/
Dsoc_pll.h22 * - PLL_INPUTDIV [20:16]
27 * The Fin = 24Mhz on Beetle
33 * PLL_INPUTDIV = R[20:16] + 1
/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/common/
DKconfig.soc93 1. Flash SPI running at 40MHz and RAM SPI running at 40MHz
94 2. Flash SPI running at 80MHz and RAM SPI running at 40MHz
95 3. Flash SPI running at 80MHz and RAM SPI running at 80MHz
97 …Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI h…
100 option to select 80MHz will only be visible if the flash SPI speed is also 80MHz.
104 bool "26MHz clock speed"
108 bool "20MHz clock speed"
112 bool "40MHz clock speed"
116 bool "80MHz clock speed"
120 bool "120MHz clock speed"
/Zephyr-Core-3.5.0/boards/arm/nucleo_h723zg/
Dnucleo_h723zg.dts49 pwms = <&pwm12 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
82 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
104 hpre = <2>; /* HCLK: 275 MHz */
105 d1ppre = <2>; /* APB1: 137.5 MHz */
106 d2ppre1 = <2>; /* APB2: 137.5 MHz */
107 d2ppre2 = <2>; /* APB3: 137.5 MHz */
108 d3ppre = <2>; /* APB4: 137.5 MHz */
/Zephyr-Core-3.5.0/dts/bindings/can/
Dti,tcan4x5x.yaml43 TCAN4x5x oscillator clock frequency in Hz (20MHz or 40MHz).
Dmicrochip,mcp251xfd.yaml69 is not set, then an internal clock (typically 40MHz or 20MHz) will be
/Zephyr-Core-3.5.0/dts/bindings/pwm/
Dnordic,nrf-sw-pwm.yaml23 TIMER: 16 MHz / 2^prescaler base clock is used for PWM generation.
39 channel-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>,
44 The above will assign P0.20 as the output for channel 0 and P1.12 as
/Zephyr-Core-3.5.0/dts/bindings/sensor/
Dti,fdc2x1x.yaml46 The internal clock oscillates at around 43360 KHz (43.36 MHz)
47 at 20 degrees Celcius.
48 Recommended external clock source frequency is 40000 KHz (40 MHz).
97 1 = 1MHz
98 4 = 3.3MHz
99 5 = 10MHz
100 7 = 33MHz
234 0.01MHz and 8.75MHz
235 2 = divide by 2. Choose for sensor frequencies between 5MHz
236 and 10MHz
[all …]
/Zephyr-Core-3.5.0/include/zephyr/drivers/pinctrl/
Dpinctrl_soc_gd32_common.h39 * - 20-25: Reserved.
107 /** Maximum 2MHz */
112 /** Maximum 10MHz */
114 /** Maximum 50MHz */
117 /** Maximum 25MHz */
119 /** Maximum 50MHz */
126 /** Maximum 10MHz */
128 /** Maximum 2MHz */
130 /** Maximum 50MHz */
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/sam3x/
DKconfig.soc49 The crystal used here can be from 3 to 20 MHz.
52 running at 12 MHz.
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/sam4e/
DKconfig.soc51 The crystal used here can be from 3 to 20 MHz.
54 running at 12 MHz.
/Zephyr-Core-3.5.0/boards/arm/legend/
Dlegend_35.overlay22 pwms = <&pwm3 3 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
28 clock-frequency = <DT_FREQ_M(24)>; /* 24MHz external clock */

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