| /Zephyr-Core-3.5.0/dts/arm/st/mp1/ |
| D | stm32mp157.dtsi | 22 #address-cells = <1>;
42 compatible = "st,stm32mp157", "st,stm32mp1", "simple-bus";
45 compatible = "st,stm32mp1-rcc";
50 compatible = "st,stm32-rcc-rctl";
51 #reset-cells = <1>;
57 compatible = "st,stm32g0-exti", "st,stm32-exti";
59 #interrupt-cells = <1>;
60 #address-cells = <1>;
71 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
72 <4 1>, <5 1>, <6 1>, <7 1>,
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/wba/ |
| D | stm32wba.dtsi | 26 #address-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <1>;
48 substate-id = <1>;
67 compatible = "st,stm32wba-hse-clock";
81 compatible = "st,stm32-lse-clock";
83 driving-capability = <1>;
96 compatible = "st,stm32wba-pll-clock";
103 compatible = "st,stm32-flash-controller", "st,stm32wba-flash-controller";
107 #address-cells = <1>;
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/h5/ |
| D | stm32h5.dtsi | 26 #address-cells = <1>;
33 #address-cells = <1>;
34 #size-cells = <1>;
47 compatible = "st,stm32-hse-clock";
53 compatible = "st,stm32h7-hsi-clock";
54 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
75 compatible = "st,stm32-lse-clock";
90 compatible = "st,stm32u5-pll-clock";
96 compatible = "st,stm32u5-pll-clock";
103 compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller";
[all …]
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| D | stm32h562.dtsi | 7 #include <st/h5/stm32h5.dtsi>
15 compatible = "st,stm32u5-pll-clock";
21 compatible = "st,stm32h562", "st,stm32h5", "simple-bus";
25 compatible = "st,stm32-gpio";
33 compatible = "st,stm32-gpio";
41 compatible = "st,stm32-gpio";
49 compatible = "st,stm32-gpio";
58 compatible = "st,stm32-uart";
67 compatible = "st,stm32-uart";
76 compatible = "st,stm32-uart";
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/l5/ |
| D | stm32l5.dtsi | 29 #address-cells = <1>;
36 #address-cells = <1>;
37 #size-cells = <1>;
51 substate-id = <1>;
76 compatible = "st,stm32-hse-clock";
96 compatible = "st,stm32-msi-clock";
103 compatible = "st,stm32-lse-clock";
118 compatible = "st,stm32l4-pll-clock";
125 compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller";
130 #address-cells = <1>;
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/u5/ |
| D | stm32u5.dtsi | 30 #address-cells = <1>;
37 #address-cells = <1>;
38 #size-cells = <1>;
52 substate-id = <1>;
77 compatible = "st,stm32-hse-clock";
97 compatible = "st,stm32u5-msi-clock";
104 compatible = "st,stm32u5-msi-clock";
111 compatible = "st,stm32-lse-clock";
126 compatible = "st,stm32u5-pll-clock";
132 compatible = "st,stm32u5-pll-clock";
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/l1/ |
| D | stm32l1.dtsi | 26 #address-cells = <1>;
43 compatible = "st,stm32-hse-clock";
56 compatible = "st,stm32l0-msi-clock";
77 compatible = "st,stm32l0-pll-clock";
85 compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
90 #address-cells = <1>;
91 #size-cells = <1>;
94 compatible = "st,stm32-nv-flash", "soc-nv-flash";
104 compatible = "st,stm32-rcc";
109 compatible = "st,stm32-rcc-rctl";
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/f2/ |
| D | stm32f2.dtsi | 27 #address-cells = <1>;
44 compatible = "st,stm32-hse-clock";
71 compatible = "st,stm32f2-pll-clock";
78 compatible = "st,stm32-flash-controller", "st,stm32f2-flash-controller";
82 #address-cells = <1>;
83 #size-cells = <1>;
86 compatible = "st,stm32-nv-flash", "soc-nv-flash";
88 write-block-size = <1>;
95 compatible = "st,stm32-rcc";
100 compatible = "st,stm32-rcc-rctl";
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/g4/ |
| D | stm32g4.dtsi | 28 #address-cells = <1>;
42 substate-id = <1>;
61 compatible = "st,stm32-hse-clock";
81 compatible = "st,stm32-lse-clock";
96 compatible = "st,stm32g4-pll-clock";
106 compatible = "st,stm32-adc";
111 #io-channel-cells = <1>;
117 st,adc-sequencer = <FULLY_CONFIGURABLE>;
121 compatible = "st,stm32-adc";
126 #io-channel-cells = <1>;
[all …]
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| D | stm32g473.dtsi | 7 #include <st/g4/stm32g491.dtsi>
11 compatible = "st,stm32g473", "st,stm32g4", "simple-bus";
14 compatible = "st,stm32-timers";
20 st,prescaler = <0>;
24 compatible = "st,stm32-pwm";
31 compatible = "st,stm32-adc";
36 #io-channel-cells = <1>;
42 st,adc-sequencer = <FULLY_CONFIGURABLE>;
46 compatible = "st,stm32-adc";
51 #io-channel-cells = <1>;
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/l4/ |
| D | stm32l4.dtsi | 28 #address-cells = <1>;
42 substate-id = <1>;
67 compatible = "st,stm32-hse-clock";
80 compatible = "st,stm32-msi-clock";
87 compatible = "st,stm32-lse-clock";
102 compatible = "st,stm32l4-pll-clock";
109 compatible = "st,stm32-flash-controller", "st,stm32l4-flash-controller";
114 #address-cells = <1>;
115 #size-cells = <1>;
118 compatible = "st,stm32-nv-flash", "soc-nv-flash";
[all …]
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| D | stm32l451.dtsi | 7 #include <st/l4/stm32l4.dtsi>
11 compatible = "st,stm32l451", "st,stm32l4", "simple-bus";
24 compatible = "st,stm32-gpio";
32 compatible = "st,stm32-gpio";
46 compatible = "st,stm32-i2c-v2";
48 #address-cells = <1>;
58 compatible = "st,stm32-i2c-v2";
60 #address-cells = <1>;
70 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
71 #address-cells = <1>;
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/f1/ |
| D | stm32f1.dtsi | 26 #address-cells = <1>;
43 compatible = "st,stm32-hse-clock";
70 compatible = "st,stm32f1-pll-clock";
78 compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
83 #address-cells = <1>;
84 #size-cells = <1>;
87 compatible = "st,stm32-nv-flash", "soc-nv-flash";
96 compatible = "st,stm32f1-rcc";
101 compatible = "st,stm32-rcc-rctl";
102 #reset-cells = <1>;
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/f0/ |
| D | stm32f0.dtsi | 26 #address-cells = <1>;
43 compatible = "st,stm32-hse-clock";
63 compatible = "st,stm32-lse-clock";
78 compatible = "st,stm32f0-pll-clock";
85 compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
90 #address-cells = <1>;
91 #size-cells = <1>;
94 compatible = "st,stm32-nv-flash", "soc-nv-flash";
103 compatible = "st,stm32f0-rcc";
108 compatible = "st,stm32-rcc-rctl";
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/f3/ |
| D | stm32f3.dtsi | 25 #address-cells = <1>;
43 compatible = "st,stm32-hse-clock";
56 compatible = "st,stm32-lse-clock";
71 compatible = "st,stm32f0-pll-clock";
78 compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
83 #address-cells = <1>;
84 #size-cells = <1>;
87 compatible = "st,stm32-nv-flash", "soc-nv-flash";
97 compatible = "st,stm32f3-rcc";
102 compatible = "st,stm32-rcc-rctl";
[all …]
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| D | stm32f302.dtsi | 7 #include <st/f3/stm32f3.dtsi>
12 compatible = "st,stm32f302", "st,stm32f3", "simple-bus";
20 compatible = "st,stm32-i2c-v2";
22 #address-cells = <1>;
29 <&rcc STM32_SRC_SYSCLK I2C2_SEL(1)>;
36 compatible = "st,stm32-i2c-v2";
38 #address-cells = <1>;
45 <&rcc STM32_SRC_SYSCLK I2C3_SEL(1)>;
52 compatible = "st,stm32-spi-fifo", "st,stm32-spi";
53 #address-cells = <1>;
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/h7/ |
| D | stm32h7.dtsi | 31 #address-cells = <1>;
38 #address-cells = <1>;
39 #size-cells = <1>;
57 #address-cells = <1>;
62 compatible = "st,stm32-hse-clock";
68 compatible = "st,stm32h7-hsi-clock";
89 compatible = "st,stm32-lse-clock";
104 compatible = "st,stm32h7-pll-clock";
109 pll2: pll@1 {
111 compatible = "st,stm32h7-pll-clock";
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/f4/ |
| D | stm32f4.dtsi | 28 #address-cells = <1>;
45 compatible = "st,stm32-hse-clock";
72 compatible = "st,stm32f4-pll-clock";
79 compatible = "st,stm32-flash-controller", "st,stm32f4-flash-controller";
83 #address-cells = <1>;
84 #size-cells = <1>;
87 compatible = "st,stm32-nv-flash", "soc-nv-flash";
89 write-block-size = <1>;
96 compatible = "st,stm32-rcc";
101 compatible = "st,stm32-rcc-rctl";
[all …]
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| D | stm32f410.dtsi | 8 #include <st/f4/stm32f4.dtsi>
16 compatible = "st,stm32f410", "st,stm32f4", "simple-bus";
19 compatible = "st,stm32-spi";
20 #address-cells = <1>;
29 compatible = "st,stm32-spi";
30 #address-cells = <1>;
39 compatible = "st,stm32-i2s";
40 #address-cells = <1>;
52 compatible = "st,stm32-i2s";
53 #address-cells = <1>;
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/f7/ |
| D | stm32f7.dtsi | 30 #address-cells = <1>;
37 #address-cells = <1>;
38 #size-cells = <1>;
58 compatible = "st,stm32-hse-clock";
71 compatible = "st,stm32-lse-clock";
86 compatible = "st,stm32f7-pll-clock";
93 compatible = "st,stm32-fmc";
99 compatible = "st,stm32-fmc-sdram";
100 #address-cells = <1>;
107 compatible = "st,stm32-flash-controller", "st,stm32f7-flash-controller";
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/wl/ |
| D | stm32wl.dtsi | 27 #address-cells = <1>;
41 substate-id = <1>;
66 compatible = "st,stm32wl-hse-clock";
81 compatible = "st,stm32-msi-clock";
88 compatible = "st,stm32-lse-clock";
103 compatible = "st,stm32wb-pll-clock";
110 compatible = "st,stm32-flash-controller", "st,stm32l4-flash-controller";
114 #address-cells = <1>;
115 #size-cells = <1>;
118 compatible = "st,stm32-nv-flash", "soc-nv-flash";
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/g0/ |
| D | stm32g0.dtsi | 3 * Copyright (c) 2019 ST Microelectronics
29 #address-cells = <1>;
43 substate-id = <1>;
62 compatible = "st,stm32-hse-clock";
68 compatible = "st,stm32g0-hsi-clock";
69 hsi-div = <1>;
76 compatible = "st,stm32-lse-clock";
91 compatible = "st,stm32g0-pll-clock";
98 compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller";
103 #address-cells = <1>;
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/l0/ |
| D | stm32l0.dtsi | 26 #address-cells = <1>;
53 compatible = "st,stm32-hse-clock";
66 compatible = "st,stm32l0-msi-clock";
73 compatible = "st,stm32-lse-clock";
88 compatible = "st,stm32l0-pll-clock";
95 compatible = "st,stm32-rtc";
103 compatible = "st,stm32-bbram";
104 st,backup-regs = <5>;
110 compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
114 #address-cells = <1>;
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/wb/ |
| D | stm32wb.dtsi | 27 #address-cells = <1>;
41 substate-id = <1>;
100 compatible = "st,stm32-msi-clock";
107 compatible = "st,stm32-lse-clock";
129 compatible = "st,stm32wb-pll-clock";
135 compatible = "st,stm32-clock-mux";
142 compatible = "st,stm32-flash-controller", "st,stm32wb-flash-controller";
147 #address-cells = <1>;
148 #size-cells = <1>;
151 compatible = "st,stm32-nv-flash", "soc-nv-flash";
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/c0/ |
| D | stm32c0.dtsi | 24 #address-cells = <1>;
41 compatible = "st,stm32-hse-clock";
47 compatible = "st,stm32c0-hsi-clock";
48 hsi-div = <1>;
55 compatible = "st,stm32-lse-clock";
71 compatible = "st,stm32-flash-controller";
76 #address-cells = <1>;
77 #size-cells = <1>;
80 compatible = "st,stm32-nv-flash", "soc-nv-flash";
90 compatible = "st,stm32f0-rcc";
[all …]
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